STM32W108HB STMicroelectronics, STM32W108HB Datasheet - Page 153

• Manufacturer Part Number: STM32W108HB
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108HB

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
10.3.2
Table 89.
31
15
30
14
Bits [6:4]
Timer x control register 2 (TIMx_CR2)
Address offset: 0xE004 (TIM1) and 0xF004 (TIM2)
Reset value:
Timer x control register 2 (TIMx_CR2)
Bit 7
29
13
TIM_TI1S: TI1 Selection
0: TI1M (input of the digital filter) is connected to TI1 input.
1: TI1M is connected to the TI_HALL inputs (XOR combination).
TIM_MMS: Master Mode Selection
This selects the information to be sent in master mode to a slave timer for synchronization
using the trigger output (TRGO).
000: Reset - the TIM_UG bit in the TMRx_EGR register is trigger output.
If the reset is generated by the trigger input (slave mode controller configured in reset mode),
then the signal on TRGO is delayed compared to the actual reset.
001: Enable - counter enable signal CNT_EN is trigger output.
This mode is used to start both timers at the same time or to control a window in which a slave
timer is enabled. The counter enable signal is generated by either the TIM_CEN control bit or
the trigger input when configured in gated mode. When the counter enable signal is controlled
by the trigger input there is a delay on TRGO except if the master/slave mode is selected (see
the TIM_MSM bit description in TMRx_SMCR register).
010: Update - update event is trigger output.
This mode allows a master timer to be a prescaler for a slave timer.
011: Compare Pulse.
The trigger output sends a positive pulse when the TIM_CC1IF flag is to be set (even if it was
already high) as soon as a capture or a compare match occurs.
100: Compare - OC1REF signal is trigger output.
101: Compare - OC2REF signal is trigger output.
110: Compare - OC3REF signal is trigger output.
111: Compare - OC4REF signal is trigger output.
28
12
Reserved
27
11
0x0000 0000
26
10
25
9
Doc ID 16252 Rev 13
24
8
Reserved
TIM_TI
1S
23
rw
7
22
6
TIM_MMS
rw
21
5
20
4
General-purpose timers
19
3
18
2
Reserved
17
1
153/232
16
0