ST72324LK2 STMicroelectronics, ST72324LK2 Datasheet
ST72324LK2
Specifications of ST72324LK2
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ST72324LK2 Summary of contents
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... Instruction Set – 8-bit Data Manipulation – 63 Basic Instructions – 17 main Addressing Modes – Unsigned Multiply Instruction Development Tools – Full hardware/software development package – In-Circuit Testing capability ST72324LJ2 ST72324LK2 ST72324LS2 Flash/ROM 8K 512 (256) LQFP32 SDIP32 400 mil 384 (256) Rev ...
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DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72324Lxx 1 DESCRIPTION The ST72F324L and ST72324BL devices are members of the ST7 microcontroller family de- signed for mid-range applications running at 3.3V. Different package options offer I/O pins. All devices are based on a common industry- ...
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PIN DESCRIPTION Figure 2. 48-Pin LQFP 7x7 Device Pinout (HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN3 / PD2 AIN4 / PD3 Legend NC = Not Connected (not bonded ...
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ST72324Lxx Figure 3. 44-Pin LQFP Package Pinout RDI / PE1 (HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 8/154 ...
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PIN DESCRIPTION (Cont’d) Figure 4. 32-Pin SDIP Package Pinout OCMP1_A / AIN10 / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 AIN12 / OCMP2_B / PC0 AIN13 / OCMP1_B / PC1 ICAP2_B / (HS) PC2 ICAP1_B / (HS) PC3 ...
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ST72324Lxx PIN DESCRIPTION (Cont’d) For more details, refer to “ELECTRICAL CHARACTERISTICS” on page 110 Legend / Abbreviations for Type input output supply In/Output level CMOS C = CMOS with input trigger T ...
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Pin n° Pin Name PC2 (HS)/ICAP2_B PC3 (HS)/ICAP1_B PC4/MISO/ICCDA PC5/MOSI/AIN14 PC6/SCK/ICCCLK PC7/SS/AIN15 ...
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ST72324Lxx are not implemented). See See “I/O PORTS” on page 40. and ISTICS for more details. 3. OSC1 and OSC2 pins connect a crystal/ceramic resonator external source to the on-chip oscil- lator; see Section 2 PIN DESCRIPTION more ...
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REGISTER & MEMORY MAP As shown in Figure 6, the MCU is capable of ad- dressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations 1024 bytes of ...
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ST72324Lxx Table 3. Hardware Register Map Register Address Block 0000h PADR 2) 0001h Port A PADDR 0002h PAOR 0003h PBDR 2) 0004h Port B PBDDR 0005h PBOR 0006h PCDR 0007h Port C PCDDR 0008h PCOR 0009h PDADR 2) 000Ah Port ...
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Register Address Block Label 0031h TACR2 0032h TACR1 0033h TACSR 0034h TAIC1HR 0035h TAIC1LR 0036h TAOC1HR 0037h TAOC1LR 0038h TIMER A TACHR 0039h TACLR 003Ah TAACHR 003Bh TAACLR 003Ch TAIC2HR 003Dh TAIC2LR 003Eh TAOC2HR 003Fh TAOC2LR 0040h 0041h TBCR2 0042h ...
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ST72324Lxx Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The ...
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FLASH PROGRAM MEMORY 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a Byte-by-Byte ba- sis using ...
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ST72324Lxx FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC Interface ICC needs a minimum of 5 and pins to be connected to the programming tool (see These pins are: – RESET: device reset – device power supply ...
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... Flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the spe- cific microcontroller device, the user needs only to implement the ICP hardware interface on the ap- ...
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ST72324Lxx 5 CENTRAL PROCESSING UNIT 5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES Enable executing 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 ...
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CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. ...
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ST72324Lxx CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh SP7 SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next ...
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SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. An overview is ...
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ST72324Lxx 6.2 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by three different source types coming from the multi- oscillator block: an external source ■ 4 crystal or ceramic resonator oscillators ■ an internal high frequency RC ...
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RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes two RE- SET sources as shown in Figure External RESET source pulse ■ Internal WATCHDOG RESET ■ These sources act on the RESET pin and it is al- ...
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ST72324Lxx 7 INTERRUPTS 7.1 INTRODUCTION The ST7 enhanced interrupt management pro- vides the following features: Hardware interrupts ■ Software interrupt (TRAP) ■ Nested or concurrent interrupt management ■ with flexible interrupt management: – software programmable nesting levels ...
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INTERRUPTS (Cont’d) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: – the highest software priority interrupt is serviced, – if ...
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ST72324Lxx INTERRUPTS (Cont’d) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see ...
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INTERRUPTS (Cont’d) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read / Write Reset Value: 111x 1010 (xAh Bit I1, I0 Software Interrupt Priority These two bits indicate the current ...
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ST72324Lxx INTERRUPTS (Cont’d) Table 8. Dedicated Interrupt Instruction Set Instruction New Description HALT Entering Halt mode IRET Interrupt routine return JRM Jump if I1:0=11 (level 3) JRNM Jump if I1:0<>11 POP CC Pop CC from the Stack RIM Enable interrupt ...
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INTERRUPTS (Cont’d) Table 9. Interrupt Mapping Source N° Block RESET Reset TRAP Software interrupt 0 Main clock controller time base inter- 1 MCC/RTC rupt 2 ei0 External interrupt port A3..0 3 ei1 External interrupt port F2..0 4 ei2 External interrupt ...
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ST72324Lxx Figure 18. External Interrupt Control bits PORT A3 INTERRUPT PAOR.3 PADDR.3 PA3 IPA BIT PORT F [2:0] INTERRUPTS PFOR.2 PFDDR.2 PF2 PORT B [3:0] INTERRUPTS PBOR.3 PBDDR.3 PB3 IPB BIT PORT B [7:4] INTERRUPTS PBOR.7 PBDDR.7 PB7 32/154 1 ...
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INTERRUPTS (Cont’d) 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read / Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 IPB IS21 IS20 Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied ...
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ST72324Lxx INTERRUPTS (Cont’d) Table 10. Nested Interrupts Register Map and Reset Values Address Register 7 (Hex.) Label 0024h I1_3 ISPR0 1 Reset Value 0025h I1_7 ISPR1 1 Reset Value 0026h ISPR2 I1_11 1 Reset Value 0027h ISPR3 Reset Value 1 ...
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POWER SAVING MODES 8.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 19): SLOW, WAIT (SLOW WAIT), AC- ...
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ST72324Lxx POWER SAVING MODES (Cont’d) 8.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During ...
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POWER SAVING MODES (Cont’d) 8.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two low- est power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruc- tion. The decision to enter either in ...
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ST72324Lxx POWER SAVING MODES (Cont’d) 8.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) ...
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POWER SAVING MODES (Cont’d) 8.4.2.1 Halt Mode Recommendations – Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O ...
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ST72324Lxx 9 I/O PORTS 9.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. An ...
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I/O PORTS (Cont’d) Figure 26. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE ( Table 11. I/O Port Mode ...
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ST72324Lxx I/O PORTS (Cont’d) Table 12. I/O Port Configurations NOT IMPLEMENTED IN V TRUE OPEN DRAIN I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V I/O PORTS PAD Notes: ...
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I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ...
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ST72324Lxx I/O PORTS (Cont’d) 9.5.1 I/O Port Implementation The I/O port register configurations are summa- rised as follows. Standard Ports PA5:4, PC7:0, PD5:0, PE1:0, PF7:6, 4 MODE floating input pull-up input open drain output push-pull output Interrupt Ports PB4, PB2:0, ...
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I/O PORTS (Cont’d) Table 14. I/O Port Register Map and Reset Values Address Register 7 (Hex.) Label Reset Value of all I/O port registers 0000h PADR 0001h PADDR MSB 0002h PAOR 0003h PBDR 0004h PBDDR MSB 0005h PBOR 0006h PCDR ...
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ST72324Lxx 10 ON-CHIP PERIPHERALS 10.1 WATCHDOG TIMER (WDG) 10.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application ...
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WATCHDOG TIMER (Cont’d) 10.1.4 How to Program the Watchdog Timeout Figure 29 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Coun- ter (CNT) and the resulting timeout duration in mil- liseconds. This can be ...
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ST72324Lxx WATCHDOG TIMER (Cont’d) Figure 30. Exact Timeout Duration (t WHERE (LSB + 128 min0 OSC2 t = 16384 x t max0 OSC2 t = 125ns MHz OSC2 OSC2 CNT = ...
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WATCHDOG TIMER (Cont’d) 10.1.5 Low Power Modes Mode Description SLOW No effect on Watchdog. WAIT No effect on Watchdog. OIE bit in WDGHALT bit MCCSR in Option register Byte 0 HALT 0 1 10.1.6 Hardware Watchdog Option If Hardware Watchdog ...
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ST72324Lxx 10.2 MAIN CLOCK CONTRO LLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) The Main Clock Controller consists of three differ- ent functions: a programmable CPU clock prescaler ■ a clock-out signal to supply external devices ■ a real time ...
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) 10.2.5 Low Power Modes Mode Description No effect on MCC/RTC peripheral. WAIT MCC/RTC interrupt cause the device to exit from WAIT mode. No effect on MCC/RTC counter (OIE bit is ACTIVE- set), ...
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ST72324Lxx MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the MCCSR register. It indicates when set that the main oscillator has reached ...
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TIMER 10.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- nals (input capture) ...
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ST72324Lxx 16-BIT TIMER (Cont’d) Figure 32. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 (Control/Status Register) ICIE OCIE TOIE FOLV2 (See note) ...
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TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read At t0 +∆t LS Byte value ...
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ST72324Lxx 16-BIT TIMER (Cont’d) Figure 33. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 34. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET ...
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TIMER (Cont’d) 10.3.3.3 Input Capture In this section, the index, i, may because there are 2 input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to ...
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ST72324Lxx 16-BIT TIMER (Cont’d) Figure 36. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 37. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER ...
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TIMER (Cont’d) 10.3.3.4 Output Compare In this section, the index, i, may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate ...
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ST72324Lxx 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written the OCiE bit is not set, the OCMPi pin ...
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TIMER (Cont’d) Figure 39. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) Figure 40. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER ...
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ST72324Lxx 16-BIT TIMER (Cont’d) 10.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the ...
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TIMER (Cont’d) Figure 41. One Pulse Mode Timing Example IC1R 01F8 COUNTER ICAP1 OCMP1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 42. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions FFFC FFFD FFFE COUNTER 34E2 OCMP1 compare2 ...
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ST72324Lxx 16-BIT TIMER (Cont’d) 10.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode ...
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TIMER (Cont’d) 10.3.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is ...
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ST72324Lxx 16-BIT TIMER (Cont’d) 10.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the ...
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TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal ...
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ST72324Lxx 16-BIT TIMER (Cont’d) CONTROL/STATUS REGISTER (CSR) Read Only (except bit 2 R/W) Reset Value: xxxx x0xx (xxh) 7 ICF1 OCF1 TOF ICF2 OCF2 TIMD Bit 7 = ICF1 Input Capture Flag input capture (reset value). 1: ...
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TIMER (Cont’d) INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). 7 MSB INPUT ...
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ST72324Lxx 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB Note: In Flash devices, ...
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ALTERNATE COUNTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. 7 MSB ALTERNATE COUNTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit ...
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ST72324Lxx 16-BIT TIMER (Cont’d) Table 18. 16-Bit Timer Register Map and Reset Values Address Register (Hex.) Label Timer A: 32 CR1 ICIE Timer B: 42 Reset Value Timer A: 31 CR2 OC1E Timer B: 41 Reset Value Timer A: 33 ...
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SERIAL PERIPHERAL INTERFACE (SPI) 10.4.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not ...
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ST72324Lxx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 44. The MOSI pins are connected together and the MISO pins are connected together. In ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM ...
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ST72324Lxx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 47). Note: The idle state of SCK must correspond to the polarity selected ...
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ST72324Lxx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.5 Error Flags 10.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: – The MODF bit is set and ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.5.4 Single Master Systems A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 49). The master device selects the individual slave de- vices by ...
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ST72324Lxx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.6 Low Power Modes Mode Description No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI oper- ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt ...
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ST72324Lxx SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Table 20. SPI Register Map and Reset Values Address Register 7 (Hex.) Label SPIDR MSB 0021h Reset Value SPICR SPIE 0022h Reset Value SPICSR SPIF 0023h Reset Value SPE SPR2 MSTR ...
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ST72324Lxx 10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) 10.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a very wide ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 50. SCI Block Diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK f CPU Read Received Data Register (RDR SCID ...
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ST72324Lxx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 50 It contains six dedicated reg- isters: – Two control registers (SCICR1 & SCICR2) – A status register (SCISR) – ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the ...
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ST72324Lxx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 52. SCI Baud Rate and Extended Prescaler Block Diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /PR /16 SCP1 CONVENTIONAL BAUD RATE ...
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ST72324Lxx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Framing Error A framing error is detected when: – The stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. – A break is received. When ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4.7 Parity Control Parity control (generation of parity bit in transmis- sion and parity checking in reception) can be ena- bled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined ...
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ST72324Lxx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4.9 Clock Deviation Causes The causes which contribute to the total deviation are: – Deviation due to transmitter error (Local TRA oscillator error of the transmitter or the trans- mitter is transmitting at ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/re- ceiving until Halt ...
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ST72324Lxx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.7 Register Description STATUS REGISTER (SCISR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (SCICR1) Read/Write Reset Value: x000 0000 (x0h SCID M WAKE Bit Receive data bit 8. This bit is used to store the 9th bit of the received ...
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ST72324Lxx SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 2 (SCICR2) Read/Write Reset Value: 0000 0000 ( TIE TCIE RIE ILIE TE Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: Interrupt is ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 The Data register performs ...
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ST72324Lxx SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 (00 h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. 7 ERPR ERPR ERPR ERPR ERPR 7 6 ...
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SERIAL COMMUNICATION INTERFACE (Cont’d) Table 23. SCI Register Map and Reset Values Address Register 7 (Hex.) Label SCISR TDRE 0050h Reset Value 1 SCIDR MSB 0051h Reset Value x SCIBRR SCP1 0052h Reset Value 0 SCICR1 R8 0053h Reset Value ...
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ST72324Lxx 10.6 10-BIT A/D CONVERTER (ADC) 10.6.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels ...
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A/D CONVERTER (ADC) (Cont’d) 10.6.3 Functional Description The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (V ) ...
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ST72324Lxx 10-BIT A/D CONVERTER (ADC) (Cont’d) 10.6.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read / Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) 7 EOC SPEED ADON 0 CH3 Bit 7 = EOC End of Conversion This bit ...
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A/D CONVERTER (Cont’d) Table 24. ADC Register Map and Reset Values Address Register 7 (Hex.) Label ADCCSR EOC 0070h Reset Value 0 ADCDRH D9 0071h Reset Value 0 ADCDRL 0072h Reset Value SPEED ADON 0 ...
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ST72324Lxx 11 INSTRUCTION SET 11.1 CPU ADDRESSING MODES The CPU features 17 different addressing modes which can be classified in seven main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) ...
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INSTRUCTION SET OVERVIEW (Cont’d) 11.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For ...
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ST72324Lxx INSTRUCTION SET OVERVIEW (Cont’d) 11.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index ...
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INSTRUCTION SET OVERVIEW (Cont’d) 11.2 INSTRUCTION GROUPS The ST 7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and ...
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ST72324Lxx INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true ...
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INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset ...
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ST72324Lxx 12 ELECTRICAL CHARACTERISTICS 12.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred default, MCU characteristics are specified for 2. 12.1.1 Minimum and Maximum values Unless otherwise specified ...
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ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 12.2.1 Voltage Characteristics Symbol ...
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ST72324Lxx 12.2.3 Thermal Characteristics Symbol T Storage temperature range STG T Maximum junction temperature (see J 12.3 OPERATING CONDITIONS Symbol Parameter f Internal clock frequency CPU Operating Voltage (ROM versions Operating Voltage (Flash versions) T Ambient temperature range ...
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SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consump- tion, the two current values must ...
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ST72324Lxx SUPPLY CURRENT CHARACTERISTICS (Cont’d) 12.4.1.1 Power Consumption vs f Figure 58. Typical I in RUN mode DD 8MHz 3000 4MHz 2MHz 2500 1MHz 2000 1500 1000 500 0 2.6 2.8 3 Vdd (V) Figure 59. Typical I SLOW mode ...
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SUPPLY CURRENT CHARACTERISTICS (Cont’d) 12.4.2 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consump- tion, ...
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ST72324Lxx 12.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 12.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = ∆t v(IT v(IT) c(INST) 12.5.2 External Clock Source Symbol ...
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CLOCK AND TIMING CHARACTERISTICS (Cont’d) 12.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external ...
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ST72324Lxx CLOCK CHARACTERISTICS (Cont’d) 12.5.4 RC Oscillators Symbol Parameter f Internal RC oscillator frequency OSC (RCINT) Note 1: To reduce disturbance to the RC oscilla- tor recommended to place decoupling capac- itors between V and V as shown ...
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CLOCK CHARACTERISTICS (Cont’d) 12.5.5 PLL Characteristics Symbol Parameter V PLL Operating Range DD(PLL) f PLL input frequency range OSC ∆ Instantaneous PLL jitter CPU CPU Note: 1. Instantaneous PLL jitter is the absolute maximum deviation on a single ...
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ST72324Lxx 12.6 MEMORY CHARACTERISTICS 12.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 12.6.2 FLASH Memory DUAL VOLTAGE HDFLASH MEMORY Symbol Parameter f Operating frequency CPU V Programming voltage Supply current ...
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EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 12.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed ...
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ST72324Lxx 12.7.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE ...
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... Dynamic latch-up class Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). ...
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ST72324Lxx 12.8 I/O PORT PIN CHARACTERISTICS 12.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys Injected Current on flash ...
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I/O PORT PIN CHARACTERISTICS (Cont’d) 12.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 67 and Figure ...
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ST72324Lxx I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 70. Typical V vs 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.6 2.8 3 Vdd (V) Figure 72. Typical V vs 3.5 3.0 2.5 2.0 1.5 2.6 2.8 3 ...
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CONTROL PIN CHARACTERISTICS 12.9.1 Asynchronous RESET Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys V Output low level voltage ...
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ST72324Lxx CONTROL PIN CHARACTERISTICS (Cont’d) 12.9.2 ICCSEL/V Pin PP Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH I Input leakage current L Figure 74. Two typical Applications ...
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TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for V Refer to I/O port characteristics for more details on the input/output alternate function characteristics (out- put compare, input capture, external clock, PWM output...). 12.10.1 16-Bit Timer Symbol Parameter t ...
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ST72324Lxx 12.11 COMMUNICATION INTERFACE CHARACTERISTICS 12.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. CPU A Symbol Parameter f SCK SPI clock frequency 1/t c(SCK) t r(SCK) SPI clock ...
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 76. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t su(SI) MOSI INPUT Figure 77. SPI Master ...
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ST72324Lxx 12.12 10-BIT ADC CHARACTERISTICS Subject to general operating conditions for V Symbol Parameter f ADC clock frequency ADC V Analog reference voltage AREF V Conversion voltage range AIN Positive input leakage current for analog input I lkg ROM devices: ...
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ADC CHARACTERISTICS (Cont’d) Figure 80. Typical A/D Converter Application R AIN V AIN 12.12.1 Analog Power Supply and Reference Pins Depending on the MCU pin count, the package may feature separate V AREF power supply pins. These pins supply power ...
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ST72324Lxx Figure 81. Power Supply Filtering 1 to 10µ POWER SUPPLY SOURCE 134/154 1 0.1µF V ST7 DIGITAL NOISE FILTERING V V 0.1µF EXTERNAL NOISE FILTERING V ST72XXX SS DD AREF SSA ...
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ADC CHARACTERISTICS (Cont’d) 12.12.3 ADC Accuracy 1) Conditions: V =3V DD Symbol Parameter Total unadjusted error Offset error Gain Error Differential linearity error D 1) ...
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ST72324Lxx 13 PACKAGE CHARACTERISTICS 13.1 PACKAGE MECHANICAL DATA Figure 83. 44-Pin Low Profile Quad Flat Package D D1 Figure 84. 48-Pin Low Profile Quad Flat Package D D1 136/154 ...
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PACKAGE MECHANICAL DATA (Cont’d) Figure 85. 32-Pin Low Profile Quad Flat Package ST72324Lxx mm inches Dim. Min Typ Max Min Typ A 1.60 A1 0.05 0.15 0.002 ...
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ST72324Lxx PACKAGE MECHANICAL DATA (Cont’d) Figure 86. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width 13.2 THERMAL CHARACTERISTICS Symbol Package thermal resistance (junction to ambient) R thJA P Power dissipation D T Maximum junction temperature Jmax Notes: ...
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SOLDERING INFORMATION In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level in- terconnect. The category of second Level Inter- connect is marked on the package and on the ...
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ST72324Lxx 14 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (FLASH) as well as in factory coded versions (ROM). ST72324BL devices are ROM versions. ST72P324L devices are Factory Advanced Service Technique ROM ...
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DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) OPTION BYTE 1 OPT7= PKG1 Pin package selection bit This option bit selects the package. Version Selected Package S/J LQFP48/LQFP44 K LQFP32 / SDIP32 Note: On the chip, each I/O port has 8 pads. ...
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... DEVICE PACKAGE VERSION 142/154 1 Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be Table 27. pleased to provide detailed information on con- tractual points. Caution: The Readout Protection binary value is inverted between ROM and FLASH products. The option byte checksum will differ between ROM and FLASH ...
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DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) Table 27. Orderable Flash Device Types Part Number Package ST72F324LK2T6 ST72F324LK4T6 ST72F324LK6T6 LQFP32 ST72F324LK2T5 ST72F324LK4T5 ST72F324LK6T5 ST72F324LK6B5 SDIP32 ST72F324LJ2T6 ST72F324LJ4T6 ST72F324LJ6T6 LQFP44 ST72F324LJ2T5 ST72F324LJ4T5 ST72F324LJ6T5 ST72F324LS2T6 LQFP48 ST72F324LS4T6 Flash Memory Temp. Range (KBytes) 8 ...
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... Reference/ROM Code *The ROM code name is assigned by STMicroelectronics. ROM code must be sent in .S19 format. .Hex extension cannot be processed. Device Type/Memory Size/Package (check only one option): ...
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... DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) 14.3 DEVELOPMENT TOOLS Development tools for the ST7 microcontrollers in- clude a complete range of hardware systems and software tools from STMicroelectronics and third- party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller pe- ripherals, develop and debug your application, and program your microcontrollers ...
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ST72324Lxx 14.3.4 Socket and Emulator Information For information on the type of socket that is sup- plied with the emulator, refer to the suggested list of sockets in Table 29. Note: Before designing the board layout rec- ommended ...
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ST7 APPLICATION NOTES Table 30. ST7 Application Notes IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 EXAMPLE DRIVERS AN 969 SCI COMMUNICATION ...
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ST72324Lxx Table 30. ST7 Application Notes IDENTIFICATION DESCRIPTION AN 978 ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE AN 985 EXECUTING CODE IN ST7 RAM AN 986 USING THE INDIRECT ADDRESSING ...
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KNOWN LIMITATIONS 15.1 ALL FLASH AND ROM DEVICES 15.1.1 Safe Connection of OSC1/OSC2 Pins The OSC1 and/or OSC2 pins must not be left un- connected otherwise the ST7 main oscillator may start and, in this configuration, could generate an ...
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ST72324Lxx 15.1.6 SCI Wrong Break duration Description A single break character is sent by setting and re- setting the SBK bit in the SCICR2 register. In some cases, the break character may have a long- er duration than expected: - ...
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OUT LD A,sema ; check the semaphore status if edge is detected CP A,#01 jrne OUT call call_routine ; call the interrupt routine OUT:LD A,#00 LD sema,A .call_routine ; entry to call_routine PUSH A PUSH X PUSH CC .ext1_rt ...
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ST72324Lxx 15.3 FLASH DEVICES ONLY 15.3.1 Timer A Restrictions in Flash Devices In Flash devices, Timer A functionality has the fol- lowing restrictions: – TAOC2HR and TAOC2LR registers are write only – Input Capture 2 is not implemented – The ...
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REVISION HISTORY Table 31. Revision History Date Revision 01-Oct-2003 1.0 First release. Changed Flash & ROM voltage range 2.85 to 3.6V in Changed OSC1 high & low level in Updated Changed I/O Port: V 01-Jan-2004 1.1 Changed Reset pin: ...
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... ST72324Lxx Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...