ST72325J4 STMicroelectronics, ST72325J4 Datasheet - Page 166

• Manufacturer Part Number: ST72325J4
• Description: 8-BIT MCU WITH 16 TO 60K FLASH/ROM, ADC, CSS, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72325J4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST72325xx
12.11 COMMUNICATION INTERFACE CHARACTERISTICS
12.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
f
Figure 90. SPI Slave Timing Diagram with CPHA=0
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
4. Depends on f
166/197
CPU
1/t
Symbol
t
t
w(SCKH)
t
w(SCKL)
t
t
t
t
t
t
t
t
dis(SO)
t
t
t
r(SCK)
f(SCK)
su(SS)
t
su(MI)
t
h(MO)
f
su(SI)
a(SO)
h(SO)
v(MO)
MISO
MOSI
h(SS)
v(SO)
h(MI)
, and T
c(SCK)
h(SI)
SCK
SS
CPHA=0
CPOL=0
CPHA=0
CPOL=1
OUTPUT
INPUT
INPUT
A
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
unless otherwise specified.
CPU
see note 2
. For example, if f
t
a(SO)
t
su(SS)
t
su(SI)
4)
Parameter
CPU
MSB IN
t
t
w(SCKH)
w(SCKL)
MSB OUT
= 8 MHz, then t
t
t
h(SI)
c(SCK)
t
DD
v(SO)
DD
,
Master
f
Slave
f
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (after enable edge)
CPU
CPU
CPU
BIT6 OUT
and 0.7xV
=8MHz
=8MHz
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
= 1 / f
3)
Conditions
CPU
DD
BIT1 IN
.
= 125 ns and t
t
h(SO)
t
t
r(SCK)
f(SCK)
su(SS)
t
f
CPU
CPU
0.0625
see I/O port pin description
LSB IN
Min
120
100
100
100
100
100
90
0
0
0
0
= 175 ns.
LSB OUT
/128
+ 50
t
h(SS)
f
f
CPU
CPU
Max
120
240
120
120
2
4
/4
/2
t
dis(SO)
t
Unit
MHz
CPU
ns
note 2
see