ST72262G1 STMicroelectronics, ST72262G1 Datasheet - Page 89

• Manufacturer Part Number: ST72262G1
• Description: 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72262G1

• 4 K Or 8 Kbytes Program Memory: ROM or single voltage extended Flash (XFlash) with read-out protection, write protection, In-Circuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt,Wait and Slow
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes

SERIAL COMMUNICATIONS INTERFACE (Cont’d)
11.5.4 Functional Description
The block diagram of the Serial Control Interface,
is shown in
isters:
– Two control registers (SCICR1 & SCICR2)
– A status register (SCISR)
– A baud rate register (SCIBRR)
– An extended prescaler receiver register (SCIER-
– An extended prescaler transmitter register (SCI-
Refer to the register descriptions in
11.5.7for the definitions of each bit.
Figure 54. Word Length Programming
PR)
ETPR)
Figure
9-bit Word length (M bit is set)
Start
Bit
8-bit Word length (M bit is reset)
Start
Bit
53. It contains 6 dedicated reg-
Bit0
Bit0
Bit1
Bit1
Break Frame
Data Frame
Idle Frame
Break Frame
Data Frame
Idle Frame
Bit2
Bit2
Bit3
Bit3
Section
Bit4
Bit4
Bit5
Bit5
11.5.4.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
Transmission and reception are driven by their
own baud rate generator.
Bit6
Bit6
ST72260Gx, ST72262Gx, ST72264Gx
Possible
Figure
Bit7
Parity
Bit7
Bit
Possible
Parity
Bit8
Bit
53).
Stop
Bit
Stop
Bit
Extra
Start
Next
Start
Bit
Bit
’1’
Extra
Next Data Frame
Next
Start
Start
Bit
Bit
’1’
Start
Bit
Next Data Frame
Start
Bit
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