ST92150JDV1TAuto STMicroelectronics, ST92150JDV1TAuto Datasheet - Page 128

• Manufacturer Part Number: ST92150JDV1TAuto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST92150JDV1TAuto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
7.3 CLOCK MANAGEMENT
The various programmable features and operating modes of the CCU are handled by four registers:
– MODER (Mode Register)
– CLKCTL (Clock Control Register)
Figure 61. Clock Control Unit Programming
128/430
9
This is a System Register (R235, Group E).
The input clock divide-by-two and the CPU clock
prescaler factors are handled by this register.
This is a Paged Register (R240, Page 55).
The low power modes, the RCCU interrupts and
the interpretation of the HALT instruction are
handled by this register.
(CLK_FLAG)
XTSTOP
oscillator
Crystal
source
CK_AF
Wait for Interrupt and Low Power Modes:
LPOWFI (CLKCTL) selects Low Power operation automatically on entering WFI mode.
WFI_CKSEL (CLKCTL) selects the CK_AF clock automatically, if present, on entering WFI mode.
XTSTOP (CLK_FLAG) automatically stops the crystal oscillator when the CK_AF clock is present and selected.
CLOCK1
CK_AF
1/2
(MODER)
DIV2
1
0
CLOCK2
6/8/10/14
MX[1:0]
PLL
x
(PLLCONF)
1/16
DX[2:0]
1/N
– CLK_FLAG (Clock Flag Register)
– PLLCONF (PLL Configuration Register)
This is a Paged Register (R242, Page 55).
This register contains various status flags, as
well as control bits for clock selection.
This is a Paged Register (R246, Page 55).
PLL management is programmed in this register.
CSU_CKSEL
(CLK_FLAG)
0
1
XT_DIV16
0
1
(CLK_FLAG)
1/4
CKAF_SEL
(CLKCTL)
CKAF_ST
0
1
CPU Clock Prescaler
Peripherals
INTCLK
CK_128
and
to