ST72264G2 STMicroelectronics, ST72264G2 Datasheet - Page 155

• Manufacturer Part Number: ST72264G2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72264G2

• 4 K Or 8 Kbytes Program Memory: ROM or single voltage extended Flash (XFlash) with read-out protection, write protection, In-Circuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt,Wait and Slow
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
13.11.2 I
Subject to general operating conditions for V
f
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
Figure 96. Typical Application with I
Notes:
1. Data based on standard I
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xV
5. At 4MHz f
t
OSC
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
t
w(SCLL)
t
su(SDA)
t
t
t
su(STA)
su(STO)
t
h(SDA)
r(SDA)
h(STA)
SDA
SCL
r(SCL)
f(SDA)
f(SCL)
I
C
, and T
2
t
C BUS
f(SDA)
b
2
C - Inter IC Control Interface
CPU
t
A
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition setup time
STOP condition setup time
STOP to START condition time (bus free)
Capacitive load for each bus line
h(STA)
unless otherwise specified.
, max.I
START
4.7kΩ
t
w(SCKH)
t
r(SDA)
2
C speed (400kHz) is not achievable. In this case, max. I
V
2
DD
C protocol requirement, not tested in production.
t
w(SCKL)
Parameter
4.7kΩ
V
DD
t
su(SDA)
2
t
r(SCK)
C Bus and Timing Diagram
100Ω
100Ω
t
h(SDA)
t
DD
f(SCK)
DD
,
SDAI
SCLI
and 0.7xV
(SDAI and SCLI). Refer to
conditions. The ST7 I
quirements of the Standard I
protocol described in the following table.
ST72XXX
Standard mode I
Min
ST72260Gx, ST72262Gx, ST72264Gx
250
0
4.7
4.0
4.0
4.7
4.0
4.7
DD
3)
.
1)
4)
2
Max
1000
C speed will be approximately 260KHz.
300
400
2
1)
C
t
su(STA)
2
C interface meets the re-
20+0.1C
20+0.1C
t
su(STO)
Min
Fast mode I
100
0
Table 26
1.3
0.6
0.6
0.6
0.6
1.3
2)
1)
t
w(STO:STA)
2
STOP
b
b
C communication
REPEATED START
Max
900
for the speed
300
300
400
2
C
5)
3)
1)
START
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Unit
pF
µs
ns
µs
µs
µs