ST72521R9 STMicroelectronics, ST72521R9 Datasheet - Page 147

• Manufacturer Part Number: ST72521R9
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72521R9

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

CONTROLLER AREA NETWORK (Cont’d)
10.8.5.3 Unexpected message transmission
Symptom:
The previous message received by pCAN, even if
this message did not pass the receive filter, will be
retransmitted by pCAN with a correct identifier and
DLC but with corrupted data. The data bytes will
be a copy of the identifier bytes IDHR and IDLR in
the following repetitive pattern:
DATA_0 = IDHR
DATA_1 = IDLR
DATA_2 = IDHR
DATA_3 = IDLR
etc.
DATA_7 = IDLR
If no message has been received before the prob-
lem occurs then identifier byte values are random
but the data bytes are in the same repetitive pat-
tern.
Details:
The buffers of the pCAN cell are configurable as
receive or transmit buffers. By default, all buffers
are configured in reception. To use a buffer to
transmit a CAN message the application has to re-
serve this buffer for transmission by setting the
LOCK bit in the BCSR register. So the buffer is
then locked for any further reception and reserved
for transmission.
Once a transmission has been requested by a
write access to data byte 7 of the buffer the appli-
cation might need to abort this transmission re-
quest. To do so, the application can reset the
LOCK bit in the BCSR register.
If the message is pending (RDY bit set) but not
currently being transmitted, then clearing the
LOCK bit will abort it immediately.
If the message is pending (RDY bit set) and cur-
rently being transmitted then the message will not
be interrupted but the CAN core will wait until the
end of this transmission attempt. Then software
must clear the LOCK bit again to abort the trans-
mission.
An unexpected transmission can occur:
IF the application resets the LOCK bit
WHILE
transmission
pending in another buffer
THEN the LOCK bit is reset but the transmission is
not stopped. Instead the content of the page 0
buffer will be transmitted.
Impact On The Application:
pCAN will echo some messages sent by other
nodes. Identifier and DLC will be correct but data
are corrupted as described previously.
Note 1: The preparation lasts two bit times just be-
fore SOF, this is the critical window during which
the LOCK bit must not be reset by the application.
the
1)
AND there is no other transmission
CAN
core
ST72F521, ST72521B
is
preparing
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the