ST72561J9 STMicroelectronics, ST72561J9 Datasheet
ST72561J9
Specifications of ST72561J9
Related parts for ST72561J9
ST72561J9 Summary of contents
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... PWM auto-reload timer with input captures independent PWM output channels, output compare and time base in- terrupt, external clock with event detector Table 1. Device Summary ST72561AR9/ST72561R9/ Features ST72561J9/ST72561K9 Program memory - bytes 60K RAM (stack) - bytes 2K (256) Operating Supply CPU Frequency Max ...
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DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72561 1 DESCRIPTION The ST72561 devices are members of the ST7 mi- crocontroller family designed for mid-range appli- cations with CAN (Controller Area Network) and LIN (Local Interconnect Network) interface. All devices are based on a common industry- standard 8-bit ...
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PIN DESCRIPTION Figure 2. LQFP 64-Pin Package Pinout OSC1 OSC2 ARTIC1 / PA0 PWM0 / PA1 PWM1 / (HS) PA2 PWM2 / PA3 PWM3 / PA4 V SS_3 V DD_3 ARTCLK / (HS) PA5 ARTIC2 / (HS) PA6 T8_OCMP2 ...
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ST72561 PIN DESCRIPTION (Cont’d) Figure 3. LQFP 44-Pin Package Pinout OSC1 OSC2 PWM0 / PA1 PWM1 / (HS) PA2 PWM2 / PA3 PWM3 / PA4 ARTCLK / (HS) PA5 ARTIC2 / (HS) PA6 T8_OCMP1 / PB1 T8_ICAP1 / PB2 MCO ...
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PIN DESCRIPTION (Cont’d) Figure 4. LQFP 32-Pin Package Pinout OSC1 OSC2 PWM0 / PA1 PWM1 / (HS) PA2 ARTCLK / (HS) PA5 T8_OCMP1 / PB1 T8_ICAP1 / PB2 MCO / PB3 For external pin connection guidelines, refer ...
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ST72561 PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to Legend / Abbreviations for Table Type input output supply In/Output level CMOS 0. TTL 0. with ...
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Pin n° Pin Name PB6 / AIN2 / T16_OCMP1 SS_2 DD_2 PB7 /AIN3 / T16_OCMP2 PC0 / AIN4 / T16_ICAP1 ...
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ST72561 Pin n° Pin Name PD4 / SCI2_RDI SSA SS_0 DDA DD_0 PD5 / SCI2_TDO ...
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REGISTER AND MEMORY MAP As shown in Figure 5, the MCU is capable of ad- dressing 64 Kbytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations Kbytes of ...
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ST72561 Register Address Block Label 000Fh PFDR 0010h Port F PFDDR 0011h PFOR 0012h to 0020h 0021h SPIDR 0022h SPI SPICR 0023h SPICSR 0024h FLASH FCSR 0025h ISPR0 0026h ISPR1 0027h ISPR2 ITC 0028h ISPR3 0029h EICR0 002Ah EICR1 002Bh ...
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Register Address Block Label 0048h SCI1ISR 0049h SCI1DR 004Ah SCI1BRR LINSCI1 004Bh SCI1CR1 (LIN Master/ 004Ch SCI1CR2 Slave) 004Dh SCI1CR3 004Eh SCI1ERPR 004Fh SCI1ETPR 0050h 0051h T16CR2 0052h T16CR1 0053h T16CSR 0054h T16IC1HR 0055h T16IC1LR 0056h T16OC1HR 0057h T16OC1LR 16-BIT ...
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ST72561 Register Address Block Label 0068h CMCR 0069h CMSR 006Ah CTSR 006Bh CTPR 006Ch CRFR 006Dh CIER 006Eh CDGR 006Fh CPSR 0070h 0071h 0072h 0073h Active CAN 0074h 0075h 0076h 0077h PAGES 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh ...
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FLASH PROGRAM MEMORY 4.1 INTRODUCTION The ST7 dual voltage High Density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a Byte-by-Byte ba- sis using ...
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ST72561 FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC INTERFACE ICC (In-Circuit Communication) needs a minimum of four and up to six pins to be connected to the programming tool (see Figure – RESET: device reset – device power supply ...
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... Flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the spe- cific microcontroller device, the user needs only to implement the ICP hardware interface on the ap- ...
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ST72561 5 CENTRAL PROCESSING UNIT 5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES Enable executing 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 ...
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CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. ...
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ST72561 CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh SP7 SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next ...
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SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example, in case of a power brown-out), and re- ducing the number of external components. An overview is ...
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ST72561 6.2 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by two different source types coming from the multi- oscillator block: an external source ■ a crystal or ceramic resonator oscillator ■ Each oscillator is optimized for ...
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RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ These sources act on ...
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ST72561 RESET SEQUENCE MANAGER (Cont’d) The RESET pin is an asynchronous signal which plays a major role in EMS performance noisy environment recommended to follow the guidelines mentioned in the electrical characteris- tics section. 6.3.3 External ...
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SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low Voltage Detector (LVD) and Auxiliary Volt- age Detector (AVD) functions managed by the SICSR register. 6.4.1 Low Voltage Detector (LVD) The Low Voltage Detector function ...
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ST72561 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between reference value and the V IT+(AVD) ply. The V reference value for falling volt- IT-(AVD) ...
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SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.3 Low Power Modes Mode Description No effect on SI. AVD interrupts cause the WAIT device to exit from Wait mode. HALT The SICSR register is frozen. 6.4.3.1 Interrupts The AVD interrupt event generates an interrupt ...
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ST72561 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read / Write Reset Value: 000x 000x (00h) 7 AVD AVD LVD Bit 7 = Reserved, must be kept cleared. Bit ...
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INTERRUPTS 7.1 INTRODUCTION The ST7 enhanced interrupt management pro- vides the following features: Hardware interrupts ■ Software interrupt (TRAP) ■ Nested or concurrent interrupt management ■ with flexible interrupt priority management: – software programmable nesting levels ...
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ST72561 INTERRUPTS (Cont’d) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: – the highest software priority interrupt is serviced, – ...
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INTERRUPTS (Cont’d) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column ...
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ST72561 INTERRUPTS (Cont’d) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read / Write Reset Value: 111x 1010 (xAh Bit I1, I0 Software Interrupt Priority These two bits indicate the ...
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INTERRUPTS (Cont’d) Table 8. Dedicated Interrupt Instruction Set Instruction New Description HALT Entering Halt mode IRET Interrupt routine return JRM Jump if I1 (level 3) JRNM Jump if I1:0 <> 11 POP CC Pop CC from the Stack ...
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ST72561 INTERRUPTS (Cont’d) Table 9. Interrupt Mapping Source N° Block RESET Reset TRAP Software interrupt 0 TLI External top level interrupt 1 MCC/RTC Main clock controller time base interrupt 2 ei0/AWUFH External interrupt ei0/ Auto wake-up from Halt 3 ei1/AVD ...
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INTERRUPTS (Cont’d) 7.6 EXTERNAL INTERRUPTS 7.6.1 I/O Port Interrupt Sensitivity The external interrupt sensitivity is controlled by the ISxx bits in the EICR register control allows up to four fully independent external interrupt source sensitivities. Each external interrupt source can ...
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ST72561 INTERRUPTS (Cont’d) 7.6.2 Register Description EXTERNAL INTERRUPT CONTROL REGISTER 0 (EICR0) Read / Write Reset Value: 0000 0000 (00h) 7 IS31 IS30 IS21 IS20 IS11 Bits 7:6 = IS3[1:0] ei3 sensitivity The interrupt sensitivity, defined using the IS3[1:0] bits, ...
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INTERRUPTS (Cont’d) Table 10. Nested Interrupts Register Map and Reset Values Address Register 7 (Hex.) Label 0025h ISPR0 I1_3 Reset Value 1 CAN TX/ER/SC 0026h ISPR1 I1_7 1 Reset Value 0027h ISPR2 I1_11 1 Reset Value 0028h ISPR3 Reset Value ...
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ST72561 8 POWER SAVING MODES 8.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, five main pow- er saving modes are implemented in the ST7 (see Figure 22): Slow ■ Wait ...
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POWER SAVING MODES (Cont’d) 8.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During WAIT ...
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ST72561 POWER SAVING MODES (Cont’d) 8.4 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) ...
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POWER SAVING MODES (Cont’d) Halt Mode Recommendations – Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as ...
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ST72561 POWER SAVING MODES (Cont’d) Figure 27. ACTIVE HALT Timing Overview ACTIVE 256 OR 4096 CYCLE RUN HALT DELAY (AFTER RESET) RESET OR HALT INTERRUPT INSTRUCTION (Active Halt enabled) Figure 28. ACTIVE HALT Mode Flow-chart OSCILLATOR HALT INSTRUCTION PERIPHERALS (MCCSR.OIE=1) ...
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POWER SAVING MODES (Cont’d) 8.6 AUTO WAKE-UP FROM HALT MODE Auto Wake-Up From Halt (AWUFH) mode is simi- lar to Halt mode with the addition of an internal RC oscillator for wake-up. Compared to ACTIVE HALT mode, AWUFH has lower ...
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ST72561 POWER SAVING MODES (Cont’d) Figure 31. AWUFH Mode Flow-chart HALT INSTRUCTION (MCCSR.OIE=0) (AWUCSR.AWUEN=1) ENABLE 0 1) WDGHALT 1 AWU RC OSC WATCHDOG MAIN OSC RESET PERIPHERALS CPU I[1:0] BITS INTERRUPT AWU RC OSC Y MAIN OSC ...
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POWER SAVING MODES (Cont’d) 8.6.1 Register Description AWUFH CONTROL/STATUS REGISTER (AWUCSR) Read / Write (except bit 2 read only) Reset Value: 0000 0000 (00h Bits 7:3 = Reserved. Bit 2 = AWUF Auto Wake-Up ...
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ST72561 9 I/O PORTS 9.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. An ...
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I/O PORTS (Cont’d) Figure 32. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE ( Table 12. I/O Port Mode ...
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ST72561 I/O PORTS (Cont’d) Table 13. I/O Port Configurations NOT IMPLEMENTED TRUE OPEN DRAIN I/O PORTS R PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V DD I/O ...
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I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ...
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ST72561 I/O PORTS (Cont’d) 9.6 I/O PORT REGISTER CONFIGURATIONS The I/O port register configurations are summa- rized as follows. 9.6.1 Standard Ports PB7:6, PC0, PC3, PC7:5, PD3:2, PD5, PE7:0, PF7:0 MODE floating input pull-up input open drain output push-pull output ...
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I/O PORTS (Cont’d) Table 14. Port Configuration Port Pin name PA0 PA1 PA2 PA3 Port A PA4 PA5 PA6 PA7 PB0 PB1 PB2 Port B PB3 PB4 PB5 PC0 PC1 PC2 Port C PC3 PC4 PC7:5 PD0 PD1 PD3:2 Port ...
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ST72561 I/O PORTS (Cont’d) Table 15. I/O Port Register Map and Reset Values Address Register 7 (Hex.) Label Reset Value 0 of all IO port registers 0000h PADR 0001h PADDR MSB 0002h PAOR 0003h PBDR 0004h PBDDR MSB 0005h PBOR ...
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ON-CHIP PERIPHERALS 10.1 WINDOW WATCHDOG (WWDG) 10.1.1 Introduction The Window Watchdog is used to detect the oc- currence of a software fault, usually generated by external interference or by unforeseen logical con- ditions, which causes the application program to ...
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ST72561 WINDOW WATCHDOG (Cont’d) The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. ...
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WINDOW WATCHDOG (Cont’d) 10.1.5 How to Program the Watchdog Timeout Figure 2 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milli- seconds. This can be used ...
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ST72561 WINDOW WATCHDOG (Cont’d) Figure 36. Exact Timeout Duration (t WHERE (LSB + 128 min0 OSC2 t = 16384 x t max0 OSC2 t = 125ns MHz OSC2 OSC2 CNT ...
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WINDOW WATCHDOG (Cont’d) Figure 37. Window Watchdog Timing Diagram T[5:0] CNT downcounter WDGWR 3Fh T6 bit Reset 10.1.6 Low Power Modes Mode Description SLOW No effect on Watchdog: The downcounter continues to decrement at normal speed. WAIT No effect on ...
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ST72561 WINDOW WATCHDOG (Cont’d) 10.1.9 Interrupts None. 10.1.10 Register Description CONTROL REGISTER (WDGCR) Read / Write Reset Value: 0111 1111 ( WDGA Bit 7 = WDGA Activation bit. This bit is set by software ...
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ON-CHIP PERIPHERALS (Cont’d) 10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK MCC/RTC The Main Clock Controller consists of three differ- ent functions: ■ a programmable CPU clock prescaler a clock-out signal to supply external devices ■ a real time clock ...
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ST72561 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) 10.2.4 Low Power Modes Mode Description No effect on MCC/RTC peripheral. WAIT MCC/RTC interrupt cause the device to exit from WAIT mode. No effect on MCC/RTC counter (OIE bit is set), ...
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has reached the ...
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ST72561 ON-CHIP PERIPHERALS (Cont’d) 10.3 PWM AUTO-RELOAD TIMER (ART) 10.3.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. These resources allow five ...
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PWM AUTO-RELOAD TIMER (Cont’d) 10.3.2 Functional Description Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every ris- ing edge of the clock signal possible to read or write ...
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ST72561 PWM AUTO-RELOAD TIMER (Cont’d) Independent PWM signal generation This mode allows up to four Pulse Width Modulat- ed signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT mode. ...
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PWM AUTO-RELOAD TIMER (Cont’d) Output compare and Time base interrupt On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generat the overflow interrupt enable bit, OIE, in the ARTCSR register, ...
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ST72561 PWM AUTO-RELOAD TIMER (Cont’d) Input Capture Function Input Capture mode allows the measurement of external signal pulse widths through ARTICRx registers. Each input capture can generate an interrupt inde- pendently on a selected input signal transition. This event is ...
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PWM AUTO-RELOAD TIMER (Cont’d) Figure 46. input Capture Timing Diagram CPU f COUNTER COUNTER 03h ARTICx PIN CFx FLAG ICRx REGISTER f CPU f COUNTER COUNTER 03h ARTICx PIN CFx FLAG ICRx REGISTER = f COUNTER CPU 04h ...
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ST72561 External Interrupt Capability This mode allows the Input capture capabilities to be used as external interrupt sources. The inter- rupts are generated on the edge of the ARTICx signal. The edge sensitivity of the external interrupts is programmable (CSx ...
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ON-CHIP PERIPHERALS (Cont’d) 10.3.3 Register Description CONTROL / STATUS REGISTER (ARTCSR) Read / Write Reset Value: 0000 0000 (00h) 7 EXCL CC2 CC1 CC0 TCE Bit 7 = EXCL External Clock This bit is set and cleared by software. It ...
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ST72561 ON-CHIP PERIPHERALS (Cont’d) PWM CONTROL REGISTER (PWMCR) Read / Write Reset Value: 0000 0000 (00h) 7 OE3 OE2 OE1 OE0 OP3 Bit 7:4 = OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or ...
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ON-CHIP PERIPHERALS (Cont’d) INPUT CAPTURE CONTROL / STATUS REGISTER (ARTICCSR) Read / Write Reset Value: 0000 0000 (00h CS2 CS1 CIE2 Bit 7:6 = Reserved, always read as 0. Bit 5:4 = CS[2:1] Capture Sensitivity These bits ...
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ST72561 PWM AUTO-RELOAD TIMER (Cont’d) Table 17. PWM Auto-Reload Timer Register Map and Reset Values Address Register 7 Label (Hex.) PWMDCR3 DC7 0031h 0 Reset Value PWMDCR2 DC7 0032h 0 Reset Value PWMDCR1 DC7 0033h 0 Reset Value PWMDCR0 DC7 ...
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TIMER 10.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- nals (input capture) ...
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ST72561 16-BIT TIMER (Cont’d) Figure 48. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 (Control/Status Register) ICIE OCIE TOIE FOLV2 (See note) ...
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TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read At t0 +Δt LS Byte value ...
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ST72561 16-BIT TIMER (Cont’d) Figure 49. Counter Timing Diagram, Internal Clock Divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 50. Counter Timing Diagram, Internal Clock Divided by 4 CPU CLOCK INTERNAL RESET ...
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TIMER (Cont’d) 10.4.3.3 Input Capture In this section, the index, i, may because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to ...
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ST72561 16-BIT TIMER (Cont’d) Figure 52. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 53. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER ...
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TIMER (Cont’d) 10.4.3.4 Output Compare In this section, the index, i, may because there are two output compare functions in the 16- bit timer. This function can be used to control an output waveform or ...
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ST72561 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written the OCiE bit is not set, the OCMPi pin ...
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TIMER (Cont’d) Figure 55. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) Figure 56. Output Compare Timing Diagram, f INTERNAL CPU CLOCK ...
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ST72561 16-BIT TIMER (Cont’d) 10.4.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the ...
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TIMER (Cont’d) Figure 57. One Pulse Mode Timing Example IC1R 01F8 COUNTER ICAP1 OCMP1 Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1 Figure 58. Pulse Width Modulation Mode Timing Example with 2 Output Compare ...
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ST72561 16-BIT TIMER (Cont’d) 10.4.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode ...
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TIMER (Cont’d) 10.4.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is ...
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ST72561 16-BIT TIMER (Cont’d) 10.4.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the ...
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TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal ...
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ST72561 16-BIT TIMER (Cont’d) CONTROL/STATUS REGISTER (CSR) Read/Write (bits 7:3 read only) Reset Value: xxxx x0xx (xxh) 7 ICF1 OCF1 TOF ICF2 OCF2 TIMD Bit 7 = ICF1 Input Capture Flag input capture (reset value ...
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TIMER (Cont’d) INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). 7 MSB INPUT ...
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ST72561 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE 2 (OC2LR) ...
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TIMER (Cont’d) Table 19. 16-Bit Timer Register Map Address Register 7 Name (Hex.) 51 CR2 OC1E 52 CR1 ICIE 53 CSR ICF1 54 IC1HR MSB 55 IC1LR MSB 56 OC1HR MSB 57 OC1LR MSB 58 CHR MSB 59 CLR ...
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ST72561 10.5 8-BIT TIMER (TIM8) 10.5.1 Introduction The timer consists of a 8-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- nals ...
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TIMER (Cont’d) Figure 59. Timer Block Diagram f CPU 1/2 COUNTER 1/4 REGISTER 1/8 f 1/8000 ALTERNATE OSC2 COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 (Control/Status Register) ICIE OCIE TOIE FOLV2 (See note) TIMER INTERRUPT ST7 ...
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ST72561 8-BIT TIMER (Cont’d) Whatever the timer mode used (input capture, out- put compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFh to 00h then: – The TOF bit of the SR ...
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TIMER (Cont’d) Figure 60. Counter Timing Diagram, Internal Clock Divided CPU INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 61. Counter Timing Diagram, Internal Clock Divided CPU INTERNAL RESET TIMER ...
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ST72561 8-BIT TIMER (Cont’d) 10.5.3.2 Input Capture In this section, the index, i, may because there are two input capture functions in the 8-bit timer. The two 8-bit input capture registers (IC1R and IC2R) are used ...
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TIMER (Cont’d) Figure 63. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 8-bit 8-bit FREE RUNNING COUNTER Figure 64. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: ...
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ST72561 8-BIT TIMER (Cont’d) 10.5.3.3 Output Compare In this section, the index, i, may because there are two output compare functions in the 8-bit timer. This function can be used to control an output waveform or ...
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TIMER (Cont’d) Notes: 1. Once the OCIE bit is set both output compare features may trigger interrupt requests. If only one is needed in the application, the interrupt routine software needs to discard the unwanted compare interrupt. This can ...
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ST72561 8-BIT TIMER (Cont’d) Figure 66. Output Compare Timing Diagram, f COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) Figure 67. Output Compare Timing Diagram, f COUNTER REGISTER OUTPUT COMPARE REGISTER ...
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TIMER (Cont’d) 10.5.3.4 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input ...
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ST72561 8-BIT TIMER (Cont’d) Figure 68. One Pulse Mode Timing Example IC1R F8 COUNTER ICAP1 OCMP1 Note: IEDG1 = 1, OC1R = D0h, OLVL1 = 0, OLVL2 = 1 Figure 69. Pulse Width Modulation Mode Timing Example COUNTER E2 OCMP1 ...
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TIMER (Cont’d) 10.5.3.5 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode uses ...
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ST72561 8-BIT TIMER (Cont’d) 10.5.4 Low Power Modes Mode No effect on 8-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 8-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode ...
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TIMER (Cont’d) 10.5.7 Register Description Each Timer is associated with three control and status registers, and with six data registers (8-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL ...
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ST72561 8-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal ...
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TIMER (Cont’d) CONTROL/STATUS REGISTER (CSR) Read Only (except bit 2 R/W) Reset Value: 0000 0000 (00h) 7 ICF1 OCF1 TOF ICF2 OCF2 TIMD Bit 7 = ICF1 Input Capture Flag input capture (reset value ...
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ST72561 8-BIT TIMER (Cont’d) INPUT CAPTURE 1 REGISTER (IC1R) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the counter value (transferred by the input capture 1 event). 7 MSB OUTPUT COMPARE 1 REGISTER (OC1R) ...
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TIMER (Cont’d) 10.5.8 8-bit Timer Register Map Address Register 7 Name (Hex.) 3C CR2 OC1E 3D CR1 ICIE 3E CSR ICF1 3F IC1R MSB 40 OC1R MSB 41 CTR MSB 42 ACTR MSB 43 IC2R MSB 44 OC2R MSB ...
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ST72561 ON-CHIP PERIPHERALS (cont’d) 10.6 SERIAL PERIPHERAL INTERFACE (SPI) 10.6.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a ...
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SERIAL PERIPHERAL INTERFACE (SPI) (cont’d) Figure 70. Serial Peripheral Interface Block Diagram SPIDR MOSI MISO 8-bit Shift Register SOD bit SCK SS Data/Address Bus Read Read Buffer 7 SPIF WCOL Write SPIE MASTER CONTROL SERIAL CLOCK GENERATOR Interrupt request SPICSR ...
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ST72561 SERIAL PERIPHERAL INTERFACE (cont’d) 10.6.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 71. The MOSI pins are connected together and the MISO pins are connected together. In ...
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SERIAL PERIPHERAL INTERFACE (cont’d) 10.6.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM ...
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ST72561 SERIAL PERIPHERAL INTERFACE (cont’d) 10.6.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: ...
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SERIAL PERIPHERAL INTERFACE (cont’d) 10.6.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 74). Note: The idle state of SCK must correspond to the polarity selected ...
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ST72561 SERIAL PERIPHERAL INTERFACE (cont’d) 10.6.5 Error Flags 10.6.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master de- vice’s SS pin is pulled low. When a Master mode fault occurs: – The MODF bit is set and ...
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SERIAL PERIPHERAL INTERFACE (cont’d) 10.6.5.4 Single Master Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured using a device as the master and ...
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ST72561 SERIAL PERIPHERAL INTERFACE (cont’d) 10.6.6 Low Power Modes Mode Description No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI oper- ...
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Register Description SPI CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL CPHA SPR1 Bit 7 = SPIE Serial Peripheral Interrupt Enable This bit is set and cleared by software. 0: Interrupt is ...
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ST72561 SERIAL PERIPHERAL INTERFACE (cont’d) SPI CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF - Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only) This bit is set ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Table 22. SPI Register Map and Reset Values Address Register 7 Label (Hex.) SPIDR MSB 21 Reset Value x SPICR SPIE 22 Reset Value 0 SPICSR SPIF 23 Reset Value ...
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ST72561 10.7 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) 10.7.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (cont’d) 10.7.4 General Description The interface is externally connected to another device by two pins: – TDO: Transmit Data Output. When the transmit- ter is disabled, the output pin returns to its I/O port configuration. When ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) Figure 77. SCI Block Diagram (in Conventional Baud Rate Generator Mode) Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL SCICR2 TIE TCIE RIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 10.7.5 SCI Mode - Functional Description Conventional Baud Rate Generator Mode The block diagram of the Serial Control Interface in conventional baud rate generator mode is shown in Figure 1. It uses four ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 10.7.5.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 10.7.5.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 10.7.5.4 Conventional Baud Rate Generation The baud rates for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: f CPU (16 PR) TR ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) Figure 79. SCI Baud Rate and Extended Prescaler Block Diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /PR /16 SCP1 ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 10.7.5.6 Receiver Muting and Wake-up Feature In multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 10.7.6 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/re- ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 10.7.8 SCI Mode Register Description STATUS REGISTER (SCISR) Read Only Reset Value: 1100 0000 (C0h TDRE TC RDRF IDLE OR Bit 7 = TDRE Transmit data register empty This bit ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) CONTROL REGISTER 1 (SCICR1) Read/Write Reset Value: x000 0000 (x0h SCID M WAKE PCE 1) This bit has a different function in LIN mode, please refer to the LIN mode ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) CONTROL REGISTER 2 (SCICR2) Read/Write Reset Value: 0000 0000 ( TIE TCIE RIE ILIE TE 1) This bit has a different function in LIN mode, please refer to the LIN ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) BAUD RATE REGISTER (SCIBRR) Read/Write Reset Value: 0000 0000 (00h) 7 SCP1 SCP0 SCT2 SCT1 SCT0 Note: When LIN slave mode is disabled, the SCI- BRR register controls the conventional baud rate generator. ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 ( ERPR ERPR ERPR ERPR ERPR Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Prescaler ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) 10.7.9 LIN Mode - Functional Description. The block diagram of the Serial Control Interface, in LIN slave mode is shown in It uses six registers: – 3 control registers: SCICR1, SCICR2 and SCICR3 – ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) Figure 80. LIN Characters 8-bit Word length (M bit is reset) Data Character Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit Idle Line LIN Synch Field Start Bit0 Bit1 Bit2 ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) Figure 81. SCI Block Diagram in LIN Slave Mode Transmit Data Register (TDR) TDO RDI TRANSMIT CONTROL SCICR2 TIE TCIE SCI INTERRUPT CONTROL f CPU LIN SLAVE BAUD RATE AUTO SYNCHRONIZATION SCIBRR LPR7 ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 10.7.9.3 LIN Reception In LIN mode the reception of a byte is the same as in SCI mode but the LINSCI has features for han- dling the LIN Header automatically (identifier de- ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 10.7.9.4 LIN Error Detection LIN Header Error Flag The LIN Header Error Flag indicates that an invalid LIN Header has been detected. When a LIN Header Error occurs: – The LHE flag is ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) If LHE bit is set due to this error during Fields other than LIN Synch Field or if LASE bit is reset then the current received Header is discarded and the SCI ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 10.7.9.5 LIN Baud Rate Baud rate programming is done by writing a value in the LPR prescaler or performing an automatic resynchronization as described below. Automatic Resynchronization To automatically adjust the baud rate ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) Figure 84. LDIV Read / Write Operations When LDUM = 0 Write LPR Write LPFR MANT(7:0) MANT(7:0) Read LPR Figure 85. LDIV Read / Write Operations When LDUM = 1 Write LPR ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 10.7.9.7 LINSCI Clock Tolerance LINSCI Clock Tolerance when unsynchronized When LIN slaves are unsynchronized (meaning no characters have been transmitted for a relatively long time), the maximum tolerated deviation of the LINSCI clock ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 10.7.9.9 Error due to LIN Synch measurement The LIN Synch Field is measured over eight bit times. This measurement is performed using a counter clocked by the CPU clock. The edge detections ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 10.7.10 LIN Mode Register Description STATUS REGISTER (SCISR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE LHE Bits 7:4 = Same function as in SCI mode; please refer to ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) CONTROL REGISTER 2 (SCICR2) Read/Write Reset Value: 0000 0000 ( TIE TCIE RIE ILIE TE Bits 7:2 Same function as in SCI mode; please re- fer to Section 0.1.8 SCI ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) SCICR2 register is set, the LHDM bit selects the Wake-Up method (replacing the WAKE bit). 0: LIN Synch Break Detection Method 1: LIN Identifier Field Detection Method Bit 2 = LHIE LIN Header ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) LIN PRESCALER FRACTION REGISTER (LPFR) Read/Write Reset Value 0000 (00h) 7 LPFR Bits 7:4 = Reserved. Bits 3:0 = LPFR[3:0] Fraction of LDIV These 4 ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) LIN HEADER LENGTH REGISTER (LHLR) Read Only Reset Value: 0000 0000 (00 h). 7 LHL7 LHL6 LHL5 LHL4 LHL3 Note: In LIN Slave mode when LASE = 1 or LHDM = 1, the ...
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ST72561 SCI™ SERIAL COMMUNICATION INTERFACE (LIN Master/Slave) (Cont’d) LIN Table 24. SCI1 Register Map and Reset Values LIN Addr. Register Name (Hex. ) SCI1SR 48 Reset Value SCI1DR 49 Reset Value SCI1BRR 4A LPR (LIN Slave Mode) Reset Value SCI1CR1 ...
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LINSCI SERIAL COMMUNICATION INTERFACE (LIN Master Only) 10.8.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d) Figure 88. SCI Block Diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI CLOCK EXTRACTION SCLK PHASE AND POLARITY CONTROL TRANSMIT CONTROL SCICR2 TIE TCIE RIE SCI INTERRUPT CONTROL ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d) 10.8.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 88 on page en dedicated registers: – Three control registers (SCICR1, SCICR2 and SCICR3) – A status ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d) 10.8.4.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d) 10.8.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d) Figure 90. SCI Baud Rate and Extended Prescaler Block Diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /PR ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d) 10.8.4.4 Conventional Baud Rate Generation The baud rates for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows : f CPU (16 PR) ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d) 10.8.4.7 Parity control Parity control (generation of parity bit in transmis- sion and parity checking in reception) can be ena- bled by setting the PCE bit in the SCICR1 register. Depending ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d) 10.8.7 SCI Synchronous Transmission The SCI transmitter allows the user to control a one way synchronous serial transmission. The SCLK pin is the output of the SCI transmitter clock. No clock pulses ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d) Figure 92. SCI Data Clock Timing Diagram ( Idle or preceding Start transmission Clock (CPOL=0, CPHA=0) Clock (CPOL=0, CPHA=1) Clock (CPOL=1, CPHA=0) Clock (CPOL=1, CPHA=1) Data Start Figure 93. ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d) 10.8.8 Register Description STATUS REGISTER (SCISR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR Bit 7 = TDRE Transmit data register empty. This bit is set by ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d) CONTROL REGISTER 1 (SCICR1) Read/Write Reset Value: x000 0000 (x0h SCID M WAKE Bit Receive data bit 8. This bit is used to store the ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d) CONTROL REGISTER 2 (SCICR2) Read/Write Reset Value: 0000 0000 ( TIE TCIE RIE ILIE TE Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d) CONTROL REGISTER 3 (SCICR3) Read/Write Reset Value: 0000 0000 (00h LINE - - CLKEN CPOL CPHA Bit 7 = Reserved, must be kept cleared. Bit 6 = LINE LIN ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d) DATA REGISTER (SCIDR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 ...
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ST72561 LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 ( ERPR ERPR ERPR ERPR ERPR Bits 7:0 = ERPR[7:0] 8-bit Extended Receive ...
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SCI™ SERIAL COMMUNICATIONS INTERFACE (LIN Master) (Cont’d) LIN Table 28. SCI2 Register Map and Reset Values LIN Address Register Name (Hex.) SCI2SR TDRE 60 Reset Value SCI2DR 61 Reset Value SCI2BRR SCP1 62 Reset Value SCI2CR1 63 Reset Value SCI2CR2 ...
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ST72561 10.9 beCAN CONTROLLER (beCAN) The beCAN controller (Basic Enhanced CAN), in- terfaces the CAN network and supports the CAN protocol version 2.0A and B. It has been designed to manage high number of incoming messages ef- ficiently with a ...
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CONTROLLER (Cont’d) CAN 2.0B Active Core The beCAN module handles the transmission and the reception of CAN messages fully autonomous- ly. Standard identifiers (11-bit) and extended iden- tifiers (29-bit) are fully supported by hardware. Control, Status and Configuration Registers ...
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ST72561 beCAN CONTROLLER (Cont’d) Figure 96. beCAN Operating Modes RESET SLEEP SLAK= 1 INAK = 0 NORMAL SLAK= 0 INAK = 0 10.9.3 Operating Modes The beCAN has three main operating modes: Ini- tialization, Normal and Sleep. After a hardware ...
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CONTROLLER (Cont’d) 10.9.3.3 Low Power Mode (Sleep) To reduce power consumption, beCAN has a low power mode called Sleep mode. This mode is en- tered on software request by setting the SLEEP bit in the CMCR register. In this ...
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ST72561 beCAN CONTROLLER (Cont’d) 10.9.3.7 Loop Back combined with Silent Mode It is also possible to combine Loop Back mode and Silent mode by setting the LBKM and SILM bits in the CDGR register. This mode can be used for ...
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CONTROLLER (Cont’d) Figure 100. Transmit Mailbox States EMPTY RQCP=X TXOK=X TME = 1 EMPTY RQCP=1 TXOK=0 TME = 1 Transmit failed * NART EMPTY RQCP=1 TXOK=1 TME = 1 TXRQ=1 PENDING RQCP=0 TXOK=0 ABRQ=1 TME = 0 Mailbox does ...
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ST72561 beCAN CONTROLLER (Cont’d) 10.9.4.2 Reception Handling For the reception of CAN messages, three mailboxes organized as a FIFO are provided. In order to save CPU load, simplify the software and guarantee data consistency, the FIFO is managed completely by ...
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CONTROLLER (Cont’d) FIFO Management Starting from the empty state, the first valid mes- sage received is stored in the FIFO which be- comes pending_1. The hardware signals the event setting the FMP[1:0] bits in the CRFR regis- ter to ...
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ST72561 beCAN CONTROLLER (Cont’d) Figure 102. Filter Bank Scale Configuration - Register Organisation Filter Bank Scale Configuration One 32-Bit Filter Identifier CFxR0 Mask/Ident. CFxR4 Bit Mapping STID10:3 Two 16-Bit Filters Identifier CFxR0 Mask/Ident. CFxR2 Identifier CFxR4 Mask/Ident. CFxR6 Bit Mapping ...
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CONTROLLER (Cont’d) Filter Bank Scale and Mode Configuration The filter banks are configured by means of the corresponding CFCRx register. To configure a fil- ter bank this must be deactivated by clearing the FACT bit in the CFCR register. ...
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ST72561 beCAN CONTROLLER (Cont’d) Figure 103. Filtering Mechanism - example Identifier Identifier Identifier Identifier Identifier Identifier Mask Identifier Mask No Match Found Message Discarded The example above shows the filtering principle of the beCAN. On reception of a message, the ...
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CONTROLLER (Cont’d) 10.9.4.4 Message Storage The interface between the software and the hard- ware for the CAN messages is implemented by means of mailboxes. A mailbox contains all infor- mation related to a message; identifier, data, con- trol and ...
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ST72561 beCAN CONTROLLER (Cont’d) Figure 104. CAN Error State Diagram ERROR ACTIVE When 128 * 11 recessive bits occur: 10.9.4.5 Error Management The error management as described in the CAN protocol is handled entirely by hardware using a Transmit Error ...
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CONTROLLER (Cont’d) 10.9.4.6 Bit Timing The bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and re- synchronizing on the following edges. Its operation may be ...
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ST72561 beCAN CONTROLLER (Cont’d) Figure 107. CAN Frames (Part Inter-Frame Space Std Arbitr. Field 12 ID Inter-Frame Space Arbitration Field 12 ID Data Frame or Remote Frame Error Frame Flag Echo Error Flag ≤ Any ...
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CONTROLLER (Cont’d) 10.9.5 Interrupts Two interrupt vectors are dedicated to beCAN. Each interrupt source can be independently ena- Figure 108. Event flags and Interrupt Generation FMP FULL FOVR EWGIE EWGF EPVIE EPVF BOFIE BOFF LECIE LECIEF RQCP TXMB 0 ...
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ST72561 beCAN CONTROLLER (Cont’d) – The FIFO interrupt can be generated by the fol- lowing events: – Reception of a new message, FMP bits in the CRFR0 register incremented. – FIFO0 full condition, FULL bit in the CRFR0 register set. ...
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CONTROLLER (Cont’d) 10.9.7 BeCAN Cell Limitations 10.9.7.1 FIFO Corruption FIFO corruption occurs in the following case: WHEN the beCAN RX FIFO already holds two messages (that is, FMP == 2) AND the application releases the FIFO (with the instruction ...
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ST72561 beCAN CONTROLLER (Cont’d) Workaround To implement the workaround, use the following sequence to release the CAN receive FIFO. This sequence replaces any occurrence of CRFR |= B_RFOM;. Figure 110. Workaround 1 if ((CRFR & 0x03) == 0x02) while (( ...
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CONTROLLER (Cont’d) In the worst case configuration, if the CAN cell speed is set to the maximum baud rate, one bit time is 8 CPU cycle. In this case the minimum time between the end of the acknowledge and ...
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ST72561 beCAN CONTROLLER (Cont’d) Side-effect of Workround 1 Because the while loop lasts 10 CPU cycles, at high baud rate possible to miss a dominant state on the bus if it lasts just one CAN bit time and ...
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Figure 114. Workaround CRFR And a,#3 Cp a,#2 Jrne _RELEASE Btjf CMSR,#5,_RELEASE ; test if reception on going. Btjf CDGR,#3,_RELEASE ; sample RX pin for 8 CAN bit time Btjf CDGR,#3,_RELEASE Btjf CDGR,#3,_RELEASE btjf CDGR,#3,_RELEASE btjf CDGR,#3,_RELEASE ...
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ST72561 beCAN CONTROLLER (Cont’d) 10.9.8 Register Description 10.9.8.1 Control and Status Registers CAN MASTER CONTROL REGISTER (CMCR) Reset Value: 0000 0010 (02h ABOM AWUM NART RFLM TXFP SLEEP INRQ Bit 7 = Reserved, must be kept cleared. Bit ...
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CONTROLLER (Cont’d) CAN MASTER STATUS REGISTER (CMSR) Reset Value: 0000 0010 (02h REC TRAN WKUI Note: To clear a bit of this register the software must write this bit with a one. Bits 7:4 = Reserved. ...
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ST72561 beCAN CONTROLLER (Cont’d) Bit 4 = TXOK0 Transmission OK for mailbox 0 - Read This bit is set by hardware when the transmission request on mailbox 0 has been completed suc- cessfully. Please refer to Figure This bit is ...
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CONTROLLER (Cont’d) CAN RECEIVE FIFO REGISTERS (CRFR) Read / Write Reset Value: 0000 0000 (00h RFOM FOVR FULL Note: To clear a bit in this register, software must write a “1” to the bit. Bits 7:6 ...
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ST72561 beCAN CONTROLLER (Cont’d) CAN ERROR STATUS REGISTER (CESR) Read / Write Reset Value: 0000 0000 (00h LEC2 LEC1 LEC0 0 Bit 7 = Reserved. Forced hardware. Bits 6:4 = LEC[2:0] Last Error Code - ...
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CONTROLLER (Cont’d) TRANSMIT ERROR COUNTER REG. (TECR) Read Only Reset Value: 00h 7 TEC7 TEC6 TEC5 TEC4 TEC3 TEC[7:0] is the least significant byte of the 9-bit Transmit Error Counter implementing part of the fault confinement mechanism of the ...
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ST72561 beCAN CONTROLLER (Cont’d) Bits 3:0 BS1[3:0] Time Segment 1 These bits define the number of time quanta in Time Segment 1 Time Segment 1 = (BS1+1) For more information on bit timing, please refer to Section 0.1.4.6 Bit Timing. ...
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CONTROLLER (Cont’d) 10.9.8.2 Mailbox Registers This chapter describes the registers of the transmit and receive mailboxes. Refer to Message Storage for detailed register mapping. Transmit and receive mailboxes have the same registers except: – MCSR register in a transmit ...
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ST72561 beCAN CONTROLLER (Cont’d) MAILBOX FILTER MATCH INDEX (MFMI) This register is read only. Reset Value: 0000 0000 (00h) 7 FMI7 FMI6 FMI5 FMI4 FMI3 Bits 7:0 = FMI[7:0] Filter Match Index This register contains the index of the filter ...