ST72561J9 STMicroelectronics, ST72561J9 Datasheet - Page 24

• Manufacturer Part Number: ST72561J9
• Description: 8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, LINSCI(TM), ACTIVE CAN
• Manufacturer: STMicroelectronics

Specifications of ST72561J9

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

ST72561
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
6.3.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until V
level specified for the selected f
A proper reset signal for a slow rising V
can generally be provided by an external RC net-
work connected to the RESET pin.
Figure 14. RESET Sequences
24/265
WATCHDOG
RESET
EXTERNAL
RESET
SOURCE
RESET PIN
V
V
IT+(LVD)
IT-(LVD)
V
RUN
DD
DD
is over the minimum
ACTIVE PHASE
OSC
RESET
LVD
frequency.
DD
supply
RUN
t
h(RSTL)in
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■
■
The device RESET pin acts as an output that is
pulled low when V
V
The LVD filters spikes on V
avoid parasitic resets.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
DD
Power-On RESET
Voltage Drop RESET
WATCHDOG UNDERFLOW
PHASE
ACTIVE
EXTERNAL
< V
RESET
IT-
(falling edge) as shown in
INTERNAL RESET (256 or 4096 T
VECTOR FETCH
RUN
w(RSTL)out
DD
ACTIVE
PHASE
WATCHDOG
< V
RESET
t
DD
w(RSTL)out
IT+
.
larger than t
(rising edge) or
RUN
Figure
CPU
Figure
)
g(VDD)
3.
3.
to