STEF05 STMicroelectronics, STEF05 Datasheet - Page 9

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STEF05

Manufacturer Part Number
STEF05
Description
Electronic fuse for 5 V line
Manufacturer
STMicroelectronics
Datasheet

Specifications of STEF05

Continuous Current (typ)
3.6 A
N-channel On-resistance (typ)
40 mΩ
Output Clamp Voltage (typ)
6.65 V
Thermal Latch (typ)
165 °C

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STEF05
5.1.2
5.1.3
5.1.4
5.1.5
5.2
5.3
Normal operating condition
The STEF05 E-fuse behaves like a mechanical fuse, buffering the circuitry on its output with
the same voltage shown at its input, with a small voltage fall due to the N-channel MOSFET
R
Output voltage clamp
This internal protection circuit clamps the output voltage to a maximum safe value, typically
6.65 V, if the input voltage exceeds this threshold.
Current limiting
When an overload event occurs, the current limiting circuit reduces the conductivity of the
power MOSFET, in order to clamp the output current at the value selected externally by
means of the limiting resistor R
Thermal shutdown
If the device temperature exceeds the thermal latch threshold, typically 165 °C, the thermal
shutdown circuitry turns the power MOSFET off, thus disconnecting the load. The EN/Fault
pin of the device is automatically set at an intermediate voltage, in order to signal the
overtemperature event. In this condition the E-fuse can be reset either by cycling the supply
voltage or by pulling down the EN pin below the V
R limit calculation
As shown in
monitor the output current and limit it at the level set by the user.
The R
following theoretical formula, together with the graph in
Equation 1
C
Connecting a capacitor between the C
output voltage ramp-up time.
Given the desired time interval Δt during which the output voltage goes from zero to its
maximum value, the capacitance to be added on the C
following theoretical formula:
Equation 2
Where C
DSOn
dv/dt
Limit
.
dv/dt
calculation
value for achieving the requested current limitation can be estimated by using the
Figure 3
is expressed in Farads and the time in seconds.
, the device uses an internal N-channel sense FET with a fixed ratio, to
C
Doc ID 019055 Rev 4
dvdt
R
Limit
Limit
=
(
Figure 3
50 10
=
dv/dt
------------- -
I
×
Short
65
pin and GND allows the modification of the
9
).
Δt 30 10
il
threshold and then releasing it.
×
dv/dt
Figure 13: Current limit vs. RLimit
12
pin can be calculated using the
Typical application
9/20
.

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