71M6541D Maxim, 71M6541D Datasheet
71M6541D
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71M6541D Summary of contents
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... Selectable Gain for One Current Input to Support Shunts • High-Speed Wh/VARh Pulse Outputs with Programmable Width • 32KB Flash, 3KB RAM (71M6541D) • 64KB Flash, 5KB RAM (71M6541F/42F) • 128KB Flash, 5KB RAM (71M6541G/42G) • Four Pulse Outputs with Pulse Count • ...
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... Data Sheet 1 Introduction ................................................................................................................................. 10 2 Hardware Description .................................................................................................................. 11 2.1 Hardware Overview............................................................................................................... 11 2.2 Analog Front End (AFE) ........................................................................................................ 12 2.2.1 Signal Input Pins ....................................................................................................... 14 2.2.2 Input Multiplexer ........................................................................................................ 15 2.2.3 Delay Compensation ................................................................................................. 19 2.2.4 ADC Pre-Amplifier ..................................................................................................... 20 2.2.5 A/D Converter (ADC) ................................................................................................. 20 2.2.6 FIR Filter ................................................................................................................... 20 2.2.7 Voltage References ................................................................................................... 20 2.2.8 71M6x01 Isolated Sensor Interface (Remote Sensor Interface) .................................. 22 2.3 Digital Computation Engine (CE) ........................................................................................... 24 2 ...
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... Application Information ............................................................................................................... 92 4.1 Connecting 5 V Devices ........................................................................................................ 92 4.2 Direct Connection of Sensors ................................................................................................ 92 4.3 71M6541D/F/G Using Local Sensors..................................................................................... 93 4.4 71M6541D/F/G Using 71M6x01and Current Shunts .............................................................. 94 4.5 71M6542F/G Using Local Sensors ........................................................................................ 95 4.6 71M6542F/G Using 71M6x01 and Current Shunts ................................................................. 96 4.7 Metrology Temperature Compensation .................................................................................. 97 4.7.1 Voltage Reference Precision ..................................................................................... 97 4.7.2 Temperature Coefficients for the 71M654x ................................................................ 97 4.7.3 Temperature Compensation for VREF with Local Sensors ......................................... 98 4 ...
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... LQFP Outline Package Drawing ................................................................... 153 6.6.2 100-Pin LQFP Package Outline Drawing ................................................................. 154 6.7 Package Markings .............................................................................................................. 155 6.8 Pinout Diagrams ................................................................................................................. 156 6.8.1 71M6541D/F/G LQFP-64 Package Pinout ............................................................... 156 6.8.2 71M6542F/G LQFP-100 Package Pinout ................................................................. 157 6.9 Pin Descriptions .................................................................................................................. 158 6.9.1 Power and Ground Pins........................................................................................... 158 6.9.2 Analog Pins ............................................................................................................. 159 6.9.3 Digital Pins .............................................................................................................. 160 6 ...
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... Figures Figure 2. 71M6541D/F/G AFE Block Diagram (Local Sensors) ............................................................... 12 Figure 3. 71M6541D/F/G AFE Block Diagram with 71M6x01.................................................................. 13 Figure 4. 71M6542F/G AFE Block Diagram (Local Sensors) .................................................................. 13 Figure 5. 71M6542F/G AFE Block Diagram with 71M6x01 ..................................................................... 14 Figure 6: States in a Multiplexer Frame (MUX_DIV[3: .................................................................. 17 Figure 7: States in a Multiplexer Frame (MUX_DIV[3: .................................................................. 17 Figure 8: General Topology of a Chopped Amplifier ...
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... Table 47: Selectable Resources using the DIO_Rn[2:0] Bits................................................................... 59 Table 48: Data/Direction Registers for SEGDIO0 to SEGDIO14 (71M6541D/F/G) .................................. 61 Table 49: Data/Direction Registers for SEGDIO19 to SEGDIO27 (71M6541D/F/G) ................................ 62 Table 50: Data/Direction Registers for SEGDIO36-39 to SEGDIO44-45 (71M6541D/F/G) ...................... 62 Table 51: Data/Direction Registers for SEGDIO51 and SEGDIO55 (71M6541D/F/G) ............................. 62 Table 52: Data/Direction Registers for SEGDIO0 to SEGDIO15 (71M6542F/G) ..................................... 63 6 Rev 2 ...
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... Table 55: Data/Direction Registers for SEGDIO51 to SEGDIO55 (71M6542F/G) ................................... 64 Table 56: LCD_VMODE[1:0] Configurations .......................................................................................... 65 Table 57: LCD Configurations ............................................................................................................... 67 Table 58: 71M6541D/F/G LCD Data Registers for SEG46 to SEG50 ..................................................... 69 Table 59: 71M6542F/G LCD Data Registers for SEG46 to SEG50 ......................................................... 70 Table 60: EECTRL Bits for 2-pin Interface ............................................................................................... 71 Table 61: EECTRL Bits for the 3-wire Interface ....................................................................................... 71 Table 62: SPI Transaction Fields ...
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... Data Sheet Table 107: LCD Driver Performance Specifications .............................................................................. 145 Table 108: LCD Driver Performance Specifications .............................................................................. 146 Table 109: VREF Performance Specifications ...................................................................................... 148 Table 110. ADC Converter Performance Specifications ....................................................................... 149 Table 111: Pre-Amplifier Performance Specifications ........................................................................... 150 Table 112: Flash Memory Timing Specifications .................................................................................. 151 Table 113 ...
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... RX TX OPTICAL OPT_RX/ INTERFACE SEGDIO55 OPT_TX/ SEGDIO51/ WPULSE/ VBIAS VARPULSE POWER FAULT WAKE DETECTION FAULTZ VSTAT * 71M6542F/G only Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet VREF V3P3A ∆Σ AD CONVERTER VBIAS FIR V3P3A - + VREF DIV MCK CK32 ADC PLL 32KHz 4.9 MHZ CKADC ...
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... Data Sheet 1 Introduction This data sheet covers the 71M6541D (32KB), 71M6541F (64KB), 71M6541G (128KB), 71M6542F (64KB), and 71M6542G (128KB) fourth generation Teridian energy measurement SoCs. The term “71M654x” is used when discussing a device feature or behavior that is applicable to all four part numbers ...
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... Resistive Shunts and Current Transformers (CT) current sensors are supported. Resistive shunt current sensors may be connected directly to the 71M654x device or isolated using a companion 71M6x01 isolator IC in order to implement a variety of single-phase / split-phase (71M6541D/F/G) or two-phase (71M6542F/G) metering configurations. An inexpensive, small size pulse transformer is used to isolate the 71M6x01 isolated sensor from the 71M654x ...
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... LINE LINE IAP Local or CT Shunt IAN VADC10 (VA) IN* IBP CT IBN *IN = Optional Neutral Current Figure 2. 71M6541D/F/G AFE Block Diagram (Local Sensors the analog input signals (IAP-IAN, VA and IBP-IBN) are Figure 2. See 2. VREF MUX CONVERTER VREF VREF VADC 71M6541D/F Figure 35 for the meter ∆ ...
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... Figure 3, when a remote isolated shunt sensor is connected via the 71M6x01, the samples associated with this current channel are not routed to the multiplexer, and are instead transferred digitally to the 71M6541D/F/G via the digital isolation interface and are directly stored in CE RAM. See ...
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... The remaining input in the 71M6541D/F/G (VA) is single-ended, and is intended for sensing the line voltage in a single-phase meter application using Equation (see 71M6542F/G features an additional single-ended voltage sensing input (VB) to support bi-phase applications using Equation 2 ...
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... When operating with local sensors, the input multiplexer sequentially applies the input signals from the analog input pins to the input of the ADC (see multiplexer frame. The multiplexer of the 71M6541D/F/G can select up to three input signals (IAP-IAN, VA, and IBP-IBN) per multiplexer frame as controlled by the I/O RAM control field MUX_DIV[3:0] (I/O RAM ...
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... Data Sheet Table 2. Required CE Code and Settings for 71M6x01 isolated Sensor I/O RAM Mnemonic FIR_LEN[1:0] ADC_DIV PLL_FAST MUX_DIV[3:0] MUX0_SEL[3:0] MUX1_SEL[3:0] MUX2_SEL[3:0] MUX3_SEL[3:0] RMT_E DIFFA_E DIFFB_E EQU[2:0] CE Code Equations Current Sensor Type Applicable Figure Notes: 1. Although not used, set to 1 (the sample data is ignored by the CE) 2 ...
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... ADC1 IBP ADC2 DIFFB_E = 1 or RMT_E = 1 IBN ADC3 VA ADC10 -- VB ADC9 -- Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Figure 3. When using one local and one remote Figure Figure 6 and Figure 7, the frame duration is 13 CK32 cycles Multiplexer Frame MUX_DIV[3: Conversions ...
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... Time_Slot_Duration * MUX_DIV] * (48+PLL_FAST*102) The ADC conversion sequence is programmable through the MUXx_SEL control fields (I/O RAM 0x2100 to 0x2105). As stated above, there are three ADC time slots in the 71M6541D/F/G and four ADC time slots in the 71M6542F/G, as set by MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). In the expression MUXx_SEL[3: ‘x’ refers to the multiplexer frame time slot number and n refers to the desired ADC input number or ADC handle (i ...
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... Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet for the settings that are applicable to the 71M6541D/F/G and Description Selects the ADC input converted during time slot 0. Selects the ADC input converted during time slot 1. ...
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... Data Sheet the current. The delay compensation implemented in the CE aligns the voltage samples with their corresponding current samples by first delaying the current samples by one full sample interval (i.e., o 360 ), then routing the voltage samples through the all-pass filter, thus delaying the voltage samples by - θ ...
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... In the second toggle state, CHOP_E[1:0] = 11, CROSS does not toggle at the end of the last multiplexer cycle in an accumulation interval. A second, low-power voltage reference is used in the LCD system and for the comparators that support transitions to and from the battery modes. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet ...
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... One 71M6x01 Isolated Sensor can be supported by the 71M6541D/F/G and 71M6542F/G. When remote interface IBP-IBN is enabled, the two analog current inputs pins IBP and IBN become a digital balanced differential interface to the remote sensor ...
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... See the 71M6xxx Data Sheet for the equation to calculate temperature from the the 71M6x01. With hardware and trim-related information on each connected 71M6x01 Isolated Sensor available to the 71M6541D/F/G, the MPU can implement temperature compensation of the energy measurement based on the individual temperature characteristics of the 71M6x01 Isolated Sensor. See Temperature Compensation ...
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... Data Sheet RST Name Address Default TMUXRB[2:0] 270A[2:0] 000 RMT_RD[15:8] 2602[7:0] RMT_RD[7:0] 2603[7:0] RFLY_DIS 210C[3] RMTB_E 2709[3] Refer to Table 76 starting on page 2.3 Digital Computation Engine (CE) The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. The CE calculations and processes include: • ...
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... No 2.3.4 Meter Equations The 71M6541D/F/G and 71M6542F/G provide hardware assistance to the CE in order to support various meter equations. This assistance is controlled through I/O RAM register EQU[2:0] (equation assist). The Compute Engine (CE) firmware for industrial configurations can implement the equations listed in EQU[2:0] specifies the equation to be used based on the meter configuration and on the number of phases used for metering ...
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... Data Sheet CK32 MUX_SYNC MUX_STATE CKTEST RTM FLAG RTM DATA0 (32 bits) RTM DATA1 (32 bits) RTM DATA2 (32 bits) RTM DATA3 (32 bits) ADC TIMING CK32 150 MUX_SYNC MUX STATE S 0 ADC EXECUTION CE TIMING 0 CE_EXECUTION CK COUNT = CE_CYCLES + 1CK for each ADC transfer ...
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... Pulse Generators The 71M6541D/F/G and 71M6542F/G provide four pulse generators, VPULSE, WPULSE, XPULSE and YPULSE, as well as hardware support for the VPULSE and WPULSE pulse generators. The pulse generators can be used to output CE status indicators, SAG for example, to DIO pins. All pulses can be configured to generate interrupts to the MPU ...
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... CE RAM location, as shown in the 71M6x01) process their corresponding sensor channels providing one sample per channel per multiplexer cycle. Figure 14 (71M6541D/F/G) and sensors (IA and IB) are connected directly to the 71M6541D/F/G as seen units of CK_FIR clock cycles based on the pulse interval T MAX PLS_MAXWIDTH[7: ...
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... IB channel is a 71M6x01 isolated sensor, the sample data does not pass through the 71M6541D/F/G multiplexer, as seen in Figure 3. In this case, the sample is taken during the second half of the multiplexer cycle and the data is directly stored in the corresponding CE RAM location as indicated in timing relationship between the remote current sensor channel and its corresponding voltage is precisely defined so that delay compensation can be properly applied by the CE ...
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... Data Sheet IA 122.07 µs CK32 (32768 Hz) MUX STATE S 0 Figure 14: Samples from Multiplexer Cycle (MUX_DIV[3: 91.5 µs CK32 (32768 Hz) MUX STATE S 0 Figure 15: Samples from Multiplexer Cycle (MUX_DIV[3: 122.07 µs Multiplexer Frame (13 x 30.518 µs = 396.7 µs -> 2520.6 Hz) ...
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... MPU Core The 71M6541D/F/G and 71M6542F/G include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 4.9 MHz clock results in a processing throughput of 4.9 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Normally, a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a single machine cycle (MPU clock cycle) ...
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... Data Sheet The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction (PDATA, SFR 0xBF, provides the upper 8 bytes for the MOVX A,@Ri instruction). ...
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... S0CON S0BUF 90 P1(DIO4:7) 88 TCON TMOD 80 P0 (DIO0:3) SP Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet shows the internal data memory map. Table 11: Internal Data Memory Map Direct Addressing Byte addressable area Bit addressable area Register banks R0…R7 Table 12. Byte Addressable X010 X011 X100 ...
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... Data Sheet 2.4.3 Generic 80515 Special Function Registers Table 13 shows the location, description and reset or power-up value of the generic 80515 SFRs. Additional descriptions of the registers can be found at the page numbers listed in the table. Table 13: Generic 80515 SFRs - Location and Reset Values ...
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... DIO as an output, while writing a 0 configures input. Writing DIO bit causes the corresponding pin high level (V3P3), while writing a 0 causes the corresponding pin to be held at a low level (GND). See 2.5.8 Digital I/O Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Function Bank selected RS1/RS0 00 ...
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... The three low order bits of the CKCON[2:0] (SFR 0x8E) register define the stretch memory cycles that are used for MOVX instructions when accessing external peripherals. The practical value of this register for the 71M6541D/F/G and 71M6542F guarantee access to XRAM between CE, MPU, and SPI. The default setting of CKCON[2:0] (001) should not be changed. ...
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... SM20 or SM21 and receive the rest of the message. The rest of the slave’s ignores the message. After addressing the slave, the host outputs the rest of the message with the 9 no additional serial port receive interrupts are generated. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 17 Table 17: Baud Rate Generation Using Timer 1 ...
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... Data Sheet UART Control Registers: The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON and S1CON shown in Table 19 and Since the TI0, RI0, TI1 and RI1 bits are in an SFR bit addressable byte, common practice would be to clear them with a bit operation, but this must be avoided ...
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... Table 23: Allowed Timer/Counter Mode Combinations Timer 0 - mode 0 Timer 0 - mode 1 Timer 0 - mode 2 Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 24, is used to select the appropriate mode. The timer/counter Function 13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 (SFR 0x8A or SFR 0x8B) register and the remaining 8 bits in the TH0 or TH1 (SFR 0x8C or SFR 0x8D) register (for Timer 0 and Timer 1, respectively) ...
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... Data Sheet Table 24: TMOD Register Bit Description (SFR 0x89) Bit Symbol Function Timer/Counter 1 If TMOD[7] is set, external input signal control is enabled for Counter 1. The TMOD[7] Gate TR1 bit in the TCON register (SFR 0x88) must also be set in order for Counter 1 to increment ...
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... IEN1[7] – IEN1[6] – IEN1[5] EX6 IEN1[4] EX5 IEN1[3] EX4 Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 26, Table 27 Table 31). Table 36). Function EAL = 0 disables all interrupts. Not used for interrupt control. Not Used. ES0 = 0 disables serial channel 0 interrupt. ET1 = 0 disables timer 1 overflow interrupt. ...
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... Data Sheet IEN1[2] EX3 IEN1[1] EX2 IEN1[0] – Table 28: The IEN2 Bit Functions (SFR 0x9A) Bit Symbol IEN2[0] ES1 Table 29: TCON Bit Functions (SFR 0x88) Bit Symbol TCON[7] TF1 TCON[6] TR1 TCON[5] TF0 TCON[4] TR0 TCON[3] IE1 TCON[2] ...
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... TF0 and TF1 (Timer 0 and Timer 1 overflow flags) are automatically cleared by hardware when the service routine is called (Signals T0ACK and T1ACK – port ISR – active high when the service routine is called). Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet 1 = External interrupt 2 occurred and has not been cleared: XPULSE, YPULSE, WPULSE or VPULSE Not used. ...
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... Data Sheet External MPU Interrupts The seven external interrupts are the interrupts external to the 80515 core, i.e., signals that originate in other parts of the 71M654x, for example the CE, DIO, RTC, or EEPROM interface. The external interrupts are connected as shown in programmable in the MPU via the I3FR and I2FR bits in T2CON (SFR 0xC8). Interrupts 2 and 3 should be programmed for falling sensitivity (I3FR = I2FR = 0) ...
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... Table 36: Interrupt Priority Registers (IP0 and IP1) Register Address Bit 7 (MSB) IP0 SFR 0xA9 – IP1 SFR 0xB9 – Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Interrupt Flag Name Location IE_SPI SFR 0xF8[7] IE_EEX SFR 0xE8[7] IE_XPULSE SFR 0xE8[6] IE_YPULSE SFR 0xE8[5] ...
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... Data Sheet Interrupt Sources and Vectors Table 38 shows the interrupts with their associated flags and vector addresses. Interrupt Request Flag IE0 TF0 IE1 TF1 RI0/TI0 RI1/TI1 IEX2 IEX3 IEX4 IEX5 IEX6 46 Table 37: Interrupt Polling Sequence External interrupt 0 Serial channel 1 interrupt ...
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... EX_SPI IE_XFER IE_RTC1S > IE_RTC1M IE_RTCT Figure 16: Interrupt Structure 71M6541D/F/G and 71M6542F/G Data Sheet ...
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... Flash Memory The device includes 128KB (71M6541G, 71M6542G), 64KB (71M6542F, 71M6541F) or 32KB (71M6541D) of on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE RAM and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations. ...
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... Write operations to page zero, whether by MPU or ICE are inhibited. The 71M6541D/F/G and 71M6542F/G also include hardware to protect against unintentional Flash write and erase. To enable flash write and erase operations, a 4-bit hardware key that must be written to the FLSH_UNLOCK[3:0] field. The key is the binary number ‘0010’. If FLSH_UNLOCK[3:0] is not ‘0010’, the Flash erase and write operation is inhibited by hardware. Proper operation of this security key requires that there be no firmware function that writes ‘ ...
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... Data Sheet 2.5.1.2 MPU/CE RAM The 71M6541D includes static RAM memory on-chip (XRAM) plus 256 bytes of internal RAM in the MPU core. The 71M6541D/F/G and the 71M6542F/G include static RAM memory on-chip (XRAM) plus 256 bytes of internal RAM in the MPU core. The static RAM is used for data storage for both MPU and CE operations ...
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... The RTC is capable of processing leap years. Each counter has its own output register. The RTC chain registers are not affected by the reset pin, watchdog timer resets transitions between the battery modes and mission mode. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 41: Clock System Summary Fixed Frequency or Range PLL_FAST=1 PLL_FAST=0 32 ...
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... Data Sheet Name Location RTC_ADJ[6:0] 2504[6:0] RTC_P[16:14] 289B[2:0] RTC_P[13:6] 289C[7:0] RTC_P[5:0] 289D[7:2] RTC_Q[1:0] 289D[1:0] RTC_RD 2890[6] RTC_WR 2890[7] RTC_FAIL 2890[4] RTC_SBSC[7:0] 2892[7:0] 2.5.4.3 RTC Rate Control Two rate adjustment mechanisms are available: • The first rate adjustment mechanism is an analog rate adjustment, using the I/O RAM register RTCA_ADJ[6:0] (I/O RAM 0x2504[6:0]), that trims the crystal load capacitance. • ...
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... See the Real Time RTC Temperature Compensation section for details. 2.5.4.4 RTC Temperature Compensation The 71M6541D/F/G and 71M6542F/G can be configured to regularly measure die temperature, including in SLP and LCD modes and while the MPU is halted. If enabled by the OSC_COMP bit, the temperature information is automatically used to correct for the temperature variation of the crystal. A table look-up method is used which generates the required digital compensation without involvement from the MPU ...
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... Data Sheet Referring to Figure 17, the table lookup method uses the 10-bits plus sign-bit value in STEMP[10:0] right- shifted by two bits to obtain an 8-bit plus sign value (i.e., NV RAM Address = STEMP/4). A limiter ensures that the resulting look-up address is in the 6-bit plus sign range of -64 to +63 (decimal). The 8-bit NV RAM content pointed to by the address is added as a 2’ ...
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... The target registers for minutes and hours are listed in Table 45: I/O RAM Registers for RTC Interrupts Name Location Rst RTC_TMIN[5:0] 289E[5:0] 0 RTC_THR[4:0] 289F[4:0] 0 Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet 22.00 22.33 0 22.65 22.98 23.31 23.64 1 23.96 24.29 … ...
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... Data Sheet 2.5.5 71M654x Temperature Sensor The 71M654x includes an on-chip temperature sensor for determining the temperature of its bandgap reference. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system for the compensation of current, voltage and energy measurement and the RTC ...
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... TEMP_BSEL bit) by setting the BCURR (I/O RAM 0x2704[3]) bit. Battery impedance can be measured by taking a battery measurement with and without BCURR. Regardless of the BCURR bit setting, the battery load is never applied in BRN, LCD, and SLP modes. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Rst Wk Dir ...
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... Refer to the 71M6xxx Data Sheet for information on reading the VCC sensor in the 71M6x01 devices. 2.5.7 UART and Optical Interface The 71M6541D/F/G and 71M6542F/G provide two asynchronous interfaces, UART0 and UART1. Both can be used to connect to AMR modules, user interfaces, etc., and also support a mechanism for programming the on-chip flash memory ...
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... Digital I/O and LCD Segment Drivers 2.5.8.1 General Information The 71M6541D/F/G and 71M6542F/G combine most DIO pins with LCD segment drivers. Each SEG/DIO pin can be configured as a DIO pin segment (SEG) driver pin. On reset or power-up, all DIO pins are DIO inputs (except for SEGDIO0-15, see caution note below) until they are configured as desired under MPU control. The pin function can be configured by the I/O RAM registers LCD_MAPn (0x2405 – ...
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... Data Sheet Value in DIO_Rn[2:0] 5 Note: Resources are selectable only on SEGDIO2 through SEGDIO11 and the PB pin. See Table 48 When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as shown in Figure 20, right), not source it from V3P3D (as shown in to the resistance of the internal switch that connects V3P3D to either V3P3SYS or VBAT ...
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... Digital I/O for the 71M6541D/F/G A total of 32 combined SEG/DIO pins plus 5 SEG outputs are available for the 71M6541D/F/G. These pins can be categorized as follows: 17 combined SEG/DIO segment pins: SEGDIO4…SEGDIO5 (2 pins) o SEGDIO9…SEGDIO14 (6 pins) o SEGDIO19…SEGDIO25 (7 pins) o SEGDIO44…SEGDIO45 (2 pins combined SEG/DIO segment pins shared with other functions: ...
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... Configuration DIO LCD – SEG Data Register – DIO Data Register – Direction Register input output Table 51: Data/Direction Registers for SEGDIO51 and SEGDIO55 (71M6541D/F/G) SEGDIO Pin # Configuration DIO LCD SEG Data Register DIO Data Register Direction Register input output 62 – ...
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... Direction Register input output P0 (SFR 0x80) Internal Resources Configurable – – (see Table 47) Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 52) is configured as a DIO output pin with a value of 1 (high) by Table Table 54. SEG46 through SEG50 cannot be configured as DIO ...
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... Data Sheet Table 53: Data/Direction Registers for SEGDIO16 to SEGDIO31 (71M6542F/G) SEGDIO 16 17 Pin # Configuration DIO LCD LCD_MAP[23:16] (I/O RAM 0x2409 SEG Data Register 16 17 DIO Data Register 16 17 Direction Register input output Table 54: Data/Direction Registers for SEGDIO32 to SEGDIO45 (71M6542F/G) ...
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... VBAT, rather than VLCD is that the LCD DAC is still active. If LCD_EXT = 1, the VLCD pin must be driven from an external source. In this case, the LCD DAC has no effect. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet 0 0 External VLCD connected to the VLCD pin. ...
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... Data Sheet The LCD system has the ability to drive up to six segments per SEG driver. If the display is configured with six back planes, the 6-way multiplexing compresses the number of SEG pins required to drive a display and therefore enhance the number of DIO pins available to the application. Refer to the LCD_MODE[2:0] field ...
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... The I/O RAM fields LCD_BLKMAP22[5:0] (I/O RAM 0x2402[5:0]) and LCD_BLKMAP23[5:0] (I/O RAM 0x2401[5:0]) identify which pixels, if any, are to blink. LCD_BLKMAP22[5:0] and LCD_BLKMAP23[5:0] are non-volatile. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 57: LCD Configurations Wk Dir Description Configures all 6 SEG/COM pins as COM. Has no effect 0 – ...
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... Data Sheet The LCD bias may be compensated for temperature using the LCD_DAC[4:0] field (I/O RAM 0x240D[4:0]). The bias may be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in MSN mode and VBAT in BRN and LCD modes). When the LCD_DAC[4:0] field is set to 000, the DAC is bypassed and powered down ...
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... LCD Drivers (71M6541D/F/G) With a maximum of 35 LCD driver pins available, the 71M6541D/F/G is capable of driving 210 pixels of an LCD display when using the 6 x multiplex mode. At eight pixels per digit, this corresponds to 26 digits. LCD segment data is written to the LCD_SEGn[5:0] I/O RAM registers as described in SEG46 through SEG50 cannot be configured as DIO pins ...
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... Pin # Configuration: SEG Data Register 2.5.9 EEPROM Interface The 71M6541D/F/G provides hardware support for either a two-pin or a three-wire (µ-wire) type of EEPROM interface. The interfaces use the SFR EECTRL (SFR 0x9F) and EEDATA (SFR 0x9E) registers for communication. 2.5.9.1 Two-pin EEPROM Interface The dedicated 2-pin serial interface communicates with external EEPROM devices and is intended for ...
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... Asserted while the serial data bus is busy. When the BUSY bit falls BUSY R INT5 interrupt occurs. Indicates that the SD signal floated to high impedance immediately 5 HiZ W after the last SDCK rising edge. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Polarity Description 0 Positive 1 when an illegal command is received. 0 Positive 1 when serial data bus is busy. 1 Positive 1 indicates that the EEPROM sent an ACK bit ...
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... Data Sheet Indicates that EEDATA (SFR 0x9E filled with data from EEPROM Specifies the number of clocks to be issued. Allowed values are 0 through 8. If RD=1, CNT bits of data are read MSB first, and right 3:0 CNT[3:0] W justified into the low order bits of EEDATA. If RD=0, CNT bits are sent MSB first to the EEPROM, shifted out of the MSB of EEDATA ...
Page 73
... The transaction ends when SPI_CSZ is raised. Some transactions may consist of a command only. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet EECTRL Byte Written CNT Cycles (0 shown) Write -- HiZ ...
Page 74
... Data Sheet When SPI_CSZ rises, SPI command bytes that are not of the form x000 0000 update the SPI_CMD (SFR 0xFD) register and then cause an interrupt to be issued to the MPU. The exception is if the transaction was a single byte. In this case, the SPI_CMD byte is always updated and the interrupt issued. SPI_CMD is not cleared when SPI_CSZ is high ...
Page 75
... Upon completion, SPI_CMD is updated to 0xxx xxxx and an SPI ByteN interrupt is generated. The exception is if the command byte is 0000 0000. In this case, no MPU interrupt is generated and SPI_CMD is not updated. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Status Byte 8 bit CMD ...
Page 76
... Data Sheet Name Location Rst 2701[7] 0 EX_SPI SPI_CMD SFR FD[7:0] – SPI_E 270C[4] 1 IE_SPI SFR F8[7] 0 270C[3] 0 SPI_SAFE 2708[7:0] 0 SPI_STAT 76 Table 64: SPI Registers Wk Dir Description 0 R/W SPI interrupt enable bit. – R SPI command. The 8-bit command from the bus master. SPI port enable bit. It enables the SPI interface on pins ...
Page 77
... In SFM mode, the MPU is completely halted. For this reason, the interrupt feature described in the SPI Transaction section above is not available in SFM mode. The 71M6541D/F/G and 71M6542F/G must be reset by the WD timer or by the RESET pin in order to exit SFM mode. ...
Page 78
... Page 73. 2.5.11 Hardware Watchdog Timer An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6541D/F/G and 71M6542F/G. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every 1.5 seconds. When not refreshed on time, the WDT overflows and the part is ...
Page 79
... Note: TMUX2[4:0] All values which are not shown are reserved. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 65: TMUX[5:0] Selections Description 32.768 kHz clock waveform Indicates when the MPU has reset the watchdog timer. Can be monitored to determine spare time in the watchdog timer. ...
Page 80
... Data Sheet 3 Functional Description 3.1 Theory of Operation The energy delivered by a power source into a load can be expressed as: Assuming phase angles are constant, the following formulae apply: Real Energy [Wh cos φ* t Reactive Energy [VARh sin φ ...
Page 81
... Behavior). From BRN mode, the part may enter either LCD mode or SLP mode, as controlled by the MPU. V3P3SYS rises LCD_ONLY LCD Figure 29: Operation Modes State Diagram Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 68). The MPU continues to execute code when 3.2.1 BRN Mode RESET MSN V3P3SYS ...
Page 82
... Data Sheet Transitions from both LCD and SLP mode to BRN mode can be initiated by the following events: • Wake-up timer timeout. • Pushbutton (PB) is activated. • A rising edge on SEGDIO4, SEGDIO52 (71M6542F/G only) or SEGDIO55. • Activity on the RX or OPT_RX pins. ...
Page 83
... XRAM undefined state, and configuration I/O RAM bits are reset (see upon wake). The data stored in non-volatile I/O RAM locations is preserved in LCD mode (the shaded locations in Table 76 are non-volatile). Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 67) including ICE, UART, Table 76 for I/O RAM state 83 ...
Page 84
... Data Sheet 3.2.3 SLP Mode When the V3P3SYS pin voltage drops below 2.8 VDC, the 71M654x enters BRN mode and the V3P3D pin obtains power from the VBAT pin instead of the V3P3SYS pin. Once in BRN mode, the MPU may invoke SLP mode by setting the SLEEP bit (I/O RAM 0x28B2[7]). The purpose of SLP mode is to consume the least amount power while still maintaining the RTC (Real Time Clock), temperature compensation of the RTC, and the non-volatile portions of the I/O RAM ...
Page 85
... SFR address 0xF9 and occupies bits [2:0], and it is read-only. In addition to the state of the main power, the VSTAT[2:0] register provides information about the internal VDD voltage under battery power. Note that if system power (V3P3A) is above 2.8 VDC, the 71M6541D/F/G and 71M6542F/G always switch from battery to system power. Description VSTAT[2:0] 000 System Power OK. V3P3A > ...
Page 86
... Data Sheet 3.3.2 IC Behavior at Low Battery Voltage When system power is not present, the 71M6541D/F/G and 71M6542F/G rely on the VBAT pin for power. If the VBAT voltage is not sufficient to maintain VDD at 2.0 VDC or greater, the MPU cannot operate reliably. Low VBAT voltage can occur while the part is operating in BRN mode, or while it is dormant in SLP or LCD mode. Two cases can be distinguished, depending on MPU code: • ...
Page 87
... WF_RX 28B3[2] EW_DIO4 WF_DIO4 28B3[1] EW_DIO52† WF_DIO52 EW_DIO55 28B3[0] WF_DIO55 Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 69. The wake flag bits are set by hardware when Table 69: Wake Enables and Flag Bits Wake Flag De-bounce Description Location 28B1[5] No 28B1[3] Yes 28B1[4] 2 µ ...
Page 88
... Data Sheet Wake Enable Name Location Name Always Enabled WF_RST Always Enabled WF_RSTBIT Always Enabled WF_ERST Always Enabled WF_OVF Always Enabled WF_CSTART Always Enabled WF_BADVDD † 71M6542F/G only. *This pin is sampled every 2 ms and must remain high for declared a valid high level. This pin is high-level sensitive ...
Page 89
... WF_ERST 28B0[3] * WF_CSTART 28B0[7] * WF_BADVDD 28B0[2] * Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 70: Wake Bits WK Dir Description Connects SEGDIO4 to the WAKE logic and permits – R/W SEGDIO4 rising to wake the part. This bit has no effect unless SEGDIO4 is configured as a digital input. Connects DIO52 to the WAKE logic and permits DIO52 high-level to wake the part (71M6542F/G only). This bit – ...
Page 90
... Data Sheet Flag WF_TMR Timer expiration WF_PB PB pin high level WF_RX Either edge RX pin WF_DIO4 SEGDIO4 rising edge WF_DIO52 SEGDIO52 high level (71M6542F/G only) If OPT_RXDIS = 1 (I/O RAM 0x2457[2]), wake on SEGDIO55 high WF_DIO55 If OPT_RXDIS = 0 wake on either edge of OPT_RX RESET pin driven high ...
Page 91
... MPU. Tying these outputs into the MPU interrupt system relieves the MPU from having to read the CESTATUS register at every occurrence of the CE_BUSY interrupt in order to detect sag or zero crossing events. Samples MUX Refer to 5.3 CE Interface Description firmware. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Pulses CE CESTATUS CECONFIG Control XRAM I/O RAM (Configuration RAM) Figure 30: MPU/CE Data Flow ...
Page 92
... Data Sheet 4 Application Information 4.1 Connecting 5 V Devices All digital input pins of the 71M654x are compatible with external 5 V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5 V devices. 4.2 Direct Connection of Sensors Figure 31 through ...
Page 93
... Using Local Sensors Figure 35 shows a 71M6541D/F/G configuration using locally connected current sensors. The IAP-IAN current channel may be directly connected to either a shunt resistor or a CT, while the IBP-IBN channel is connected and is therefore isolated. This configuration implements a single-phase measurement with tamper-detection using one current sensor to measure the neutral current. This configuration can also be used to create a split phase meter (e ...
Page 94
... AFE configuration corresponding to Shunt NEUTRAL Shunt LINE TERIDIAN 71M6xx1 Pulse Trans- former AMR IR HOST Figure 36: 71M6541D/F/G with 71M6x01 isolated Sensor 94 Figure 36. LOAD Note: This system is referenced to LINE NEUTRAL POWER SUPPLY LINE MUX and ADC V3P3A V3P3SYS GNDA GNDD PWR MODE ...
Page 95
... CT or Shunt PHASE A NEUTRAL Shunt PHASE B AMR IR HOST Figure 37: 71M6542F/G with Local Sensors Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Figure 4 for the AFE configuration corresponding to LOAD Note: LOAD This system is referenced to PHASE A NEUTRAL POWER SUPPLY PHASE A MUX and ADC V3P3A V3P3SYS ...
Page 96
... Data Sheet 4.6 71M6542F/G Using 71M6x01 and Current Shunts Figure 38 shows a typical two-phase connection for the 71M6542F/G using one isolated and one non- isolated sensor. For best performance, the IAP-IAN current sensor input is configured for differential mode (i.e., DIFFA_E = 1, I/O RAM 0x210C[4]). The 71M6x01 Isolated Sensor Interface is used to isolate phase B. ...
Page 97
... See 4.7.1 Voltage Reference TC The coefficients multiplying TC1 and TC2 to obtain PPMC and PPMC2 are derived from the 1.195V ADC voltage reference and scaling performed in the CE, as shown above. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet ⋅ ...
Page 98
... Data Sheet See 4.7.3 and 4.7.4 below for further temperature compensation details. 4.7.3 Temperature Compensation for VREF with Local Sensors This section discusses metrology temperature compensation for the meter designs where local sensors are used, as shown in Figure 35 In these configurations where all sensors are directly connected to the 71M654x, each sensor channel’s accuracy is affected by the voltage variation in the 71M654x VREF due to temperature ...
Page 99
... GAIN_ADJ0 compensates for the VA and VB (71M6542F/G only) voltage measurements in the 71M654x and is used to compensate the VREF in the 71M654x. The designer may optionally add Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet 38, the VA voltage sensor is available in both the 71M6541D/F/G and ⋅ ⋅ 10 TEMP ...
Page 100
... Data Sheet compensation for the resistive voltage dividers into the PPMC and PPMC2 coefficients for this channel. • GAIN_ADJ1 provides compensation for the IA current channel and compensates for the 71M654x VREF. The designer may optionally add compensation for the shunt and its corresponding signal conditioning circuit into the PPMC and PPMC2 coefficients for this channel. • ...
Page 101
... It may need an analog filter when receiving modulated optical signals. With modulation, an optical emitter can be operated at higher current than nominal, enabling it to increase the distance along the optical path. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet 10 k Ω Ω EEPROM ...
Page 102
... For a production meter, the RESET pin should be protected by the external components shown in Figure 42, right side. R1 should be in the range of 100Ω and mounted as closely as possible to the IC. Since the 71M6541D/F/G and 71M6542F/G generate their own power-on reset, a reset button or circuitry, as shown in Figure 42, is only required for test units and prototypes ...
Page 103
... V3P3D 62 Ω 62 Ω 62 Ω Figure 43: External Components for the Emulator Interface Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet LCD Segments (optional) 71M654x ICE_E E_RST E_RXT E_TCLK 103 ...
Page 104
... Crystal Oscillator The oscillator of the 71M6541D/F/G and 71M6542F/G drives a standard 32.768 kHz watch crystal. The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to the VBAT_RTC pin ...
Page 105
... DIFFA_E R R TMUXRB[2: MUX_DIV[3:0] MUX9_SEL MUX7_SEL MUX5_SEL MUX3_SEL MUX1_SEL OSC_COMP TEMP_BAT TBYTE_BUSY LCD_MODE[2:0] LCD_ALLCOM R LCD_MAP[55:48] 71M6541D/F/G and 71M6542F/G Data Sheet are an alternative sequential address to the addresses Bit 3 Bit 2 Bit 1 CHOP_E[1:0] RTM_E SUM_SAMPS[12:8] CE_LCTN[5:0] RFLY_DIS FIR_LEN[1:0] RMT_E TMUXRA[2: MUX10_SEL ...
Page 106
... Data Sheet Name Addr Bit 7 LCD_MAP5 2015 LCD_MAP4 2016 LCD_MAP3 2017 LCD_MAP2 2018 LCD_MAP1 2019 LCD_MAP0 201A DIO_R5 201B U DIO_R4 201C U DIO_R3 201D U DIO_R2 201E U DIO_R1 201F U DIO_R0 2020 U DIO0 2021 DIO_EEX[1:0] DIO1 2022 DIO_PW DIO_PV DIO2 2023 ...
Page 107
... PLS_MAXWIDTH[7:0] PLS_INTERVAL[7:0] R DIFFB_E DIFFA_E RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] U ADC_DIV PLL_FAST TRIMT[7:0] LCD_MODE[2:0] LCD_ALLCOM R LCD_MAP[55:48] LCD_MAP[47:40] 71M6541D/F/G and 71M6542F/G Data Sheet Bit 3 Bit 2 Bit 1 MUX10_SEL[3:0] MUX8_SEL[3:0] MUX6_SEL[3:0] MUX4_SEL[3:0] MUX2_SEL[3:0] MUX0_SEL[3:0] CHOP_E[1:0] RTM_E SUM_SAMPS[12:8] CE_LCTN[5:0] RFLY_DIS FIR_LEN[1: RTM0[9:8] RESET MPU_DIV[2:0] LCD_Y ...
Page 108
... Data Sheet Name Addr Bit 7 LCD_MAP4 2407 LCD_MAP3 2408 LCD_MAP2 2409 LCD_MAP1 240A LCD_MAP0 240B LCD4 240C U LCD_DAC 240D U SEGDIO0 2410 U … … U SEGDIO15 241F U SEGDIO16 2420 U … … U SEGDIO45 243D U SEGDIO46 243E U … … U SEGDIO50 2442 U SEGDIO51 ...
Page 109
... PORT_E SPI_E NVRAM[0] – NVRAM[7F] – Direct Access WAKE_TMR[7:0] STEMP[10:3] U BSENSE[7:0] LKPADDR[6:0] LKPDAT[7: RTC_FAIL 71M6541D/F/G and 71M6542F/G Data Sheet Bit 3 Bit 2 Bit 1 TMUX2[4:0] U EX_RTC1M EX_RTC1S FLSH_RDE FLSH_WRE BCURR SPARE[2:0] INT3 INT2 INT1 IE_RTC1S U IE_RTC1M ...
Page 110
... Data Sheet Name Addr Bit 7 RTC2 2892 RTC3 2893 U RTC4 2894 U RTC5 2895 U RTC6 2896 U RTC7 2897 U RTC8 2898 U RTC9 2899 RTC10 289B U RTC11 289C RTC12 289D RTC13 289E U RTC14 289F U TEMP 28A0 TEMP_BSEL TEMP_PWR WF1 28B0 WF_CSTART ...
Page 111
... MUXSYNC according to the value in CHOP_E R toggle 01 = positive 1 except at the mux sync edge at the end of an accumulation interval. 71M6541D/F/G and 71M6542F/G Data Sheet PLL_FAST = 0 PLL_FAST = 1 6.291456 MHz 19.660800 MHz 1.572864 MHz 4.9152 MHz 0.786432 MHz 2.4576 MHz 2 ...
Page 112
... Data Sheet Name Location CHOPR[1:0] 2709[7:6] DIFFA_E 210C[4] 210C[5] DIFFB_E DIO_R2[2:0] 2455[2:0] DIO_R3[2:0] 2455[6:4] 2454[2:0] DIO_R4[2:0] 2454[6:4] DIO_R5[2:0] DIO_R6[2:0] 2453[2:0] DIO_R7[2:0] 2453[6:4] DIO_R8[2:0] 2452[2:0] DIO_R9[2:0] 2452[6:4] DIO_R10[2:0] 2451[2:0] 2451[6:4] DIO_R11[2:0] 2450[2:0] DIO_RPB[2:0] DIO_DIR[15:12] SFR B0[7:4] DIO_DIR[11:8] SFR A0[7:4] DIO_DIR[7:4] SFR 90[7:4] ...
Page 113
... VA*(IA-IB)/ element, 3W 1φ VA*IA + VB*IB † element, 3W 3φ Delta Note: 1. Optionally, IB may be used to measure neutral current. † 71M6542F/G only 71M6541D/F/G and 71M6542F/G Data Sheet Reset Polarity Description State 1 when an illegal command 0 Positive is received. 0 Positive 1 when serial data bus is busy. 1 indicates that the ...
Page 114
... Data Sheet Name Location EX_XFER 2700[0] EX_RTC1S 2700[1] EX_RTC1M 2700[2] EX_RTCT 2700[3] EX_SPI 2701[7] EX_EEX 2700[7] EX_XPULSE 2700[6] EX_YPULSE 2700[5] EX_WPULSE 2701[6] 2701[5] EX_VPULSE EW_DIO4 28B3[2] EW_DIO52 28B3[1] EW_DIO55 28B3[0] EW_PB 28B3[3] 28B3[4] EW_RX FIR_LEN[1:0] 210C[2:1] 114 Rst Wk Dir Description Interrupt enable bits ...
Page 115
... Indicates that the flash may be read by ICE or SPI slave. FLSH_RDE = – – R (!SECURE) Must be a ‘2’ to enable any flash modification. See the description of Flash 0 0 R/W security for more details. – – R Indicates that the flash may be written through ICE or SPI slave ports. 71M6541D/F/G and 71M6542F/G Data Sheet 115 ...
Page 116
... Data Sheet Name Location IE_XFER SFR E8[0] IE_RTC1S SFR E8[1] IE_RTC1M SFR E8[2] IE_RTCT SFR E8[4] IE_SPI SFR F8[7] IE_EEX SFR E8[7] IE_XPULSE SFR E8[6] IE_YPULSE SFR E8[5] IE_WPULSE SFR F8[4] SFR F8[3] IE_VPULSE INTBITS 2707[6:0] LCD_ALLCOM 2400[3] LCD_BAT 2402[7] LCD_BLNKMAP23[5:0] 2401[5:0] LCD_BLNKMAP22[5:0] 2402[5:0] LCD_CLK[1:0] 2400[1:0] LCD_DAC[4:0] 240D[4:0] ...
Page 117
... SEG and DIO data for SEGDIO51 through SEGDIO55. If configured as DIO, bit 1 is direction (1 is output input), bit 0 is data, and the other bits are 0 – R/W ignored. SEGDIO52 through SEDIO54 are available only on the 71M6542F/G. 71M6541D/F/G and 71M6542F/G Data Sheet Output LCD_MODE 100 Static display 101 5 states, 1/3 bias ...
Page 118
... Data Sheet Name Location LCD_VMODE[1:0] 2401[7:6] LCD_Y 2400[2] LKPADDR[6:0] 2887[6:0] LKPAUTOI 2887[7] LKPDAT[7:0] 2888[7:0] LKP_RD 2889[1] LKP_WR 2889[0] MPU_DIV[2:0] 2200[2:0] MUX0_SEL[3:0] 2105[3:0] MUX1_SEL[3:0] 2105[7:4] MUX2_SEL[3:0] 2104[3:0] MUX3_SEL[3:0] 2104[7:4] 2103[3:0] MUX4_SEL[3:0] MUX5_SEL[3:0] 2103[7:4] MUX6_SEL[3:0] 2102[3:0] MUX7_SEL[3:0] 2102[7:4] 2101[3:0] MUX8_SEL[3:0] ...
Page 119
... The IC sets these bits to indicate that a parity error on the remote sensor has been detected. Once set, the bits are remembered until they are cleared R/W the MPU Indicates that the clock generation PLL is settled. 71M6541D/F/G and 71M6542F/G Data Sheet under the “Bit Banged Optical UART page 58. 119 ...
Page 120
... Data Sheet Name Location 2200[4] PLL_FAST PLS_MAXWIDTH[7:0] 210A[7:0] PLS_INTERVAL[7:0] 210B[7:0] PLS_INV 210C[0] PORT_E 270C[5] PRE_E 2704[5] SFRB2[7] PREBOOT RCMD[4:0] SFR FC[4:0] RESET 2200[3] RFLY_DIS 210C[3] 120 Rst Wk Dir Description Controls the speed of the PLL and MCK R 19.66 MHz (XTAL * 600 ...
Page 121
... DAY (01 = Sunday) – – DATE – – – – Each write operation to one of these registers must be preceded by a write to 0x20A0. 40 – R/W Analog RTC frequency adjust register. 71M6541D/F/G and 71M6542F/G Data Sheet (RTC). (RTC). 121 ...
Page 122
... Data Sheet Name Location RTM_E 2106[1] RTM0[9:8] 210D[1:0] RTM0[7:0] 210E[7:0] 210F[7:0] RTM1[7:0] RTM2[7:0] 2110[7:0] RTM3[7:0] 2111[7:0] SFR B2[6] SECURE SLEEP 28B2[7] SPI_CMD[7:0] SFR FD[7:0] SPI_E 270C[4] SPI_SAFE 270C[3] SPI_STAT[7:0] 2708[7:0] STEMP[10:3] 2881[7:0] STEMP[2:0] 2882[7:5] SUM_SAMPS[12:8] 2107[4:0] SUM_SAMPS[7:0] 2108[7:0] TBYTE_BUSY 28A0[3] ...
Page 123
... Silicon Version VERSION[7:0] 0001 0011 B01 0010 0010 B02 Brings the ADC reference voltage out to the VREF pin. This feature is disabled 0 0 R/W when VREF_DIS= R/W Disables the internal ADC voltage reference. 71M6541D/F/G and 71M6542F/G Data Sheet 2.5.12 for details. 2.5.12 for details. 123 ...
Page 124
... Data Sheet Name Location VSTAT[2:0] SFR F9[2:0] WAKE_ARM 28B2[5] 2880[7:0] WAKE_TMR[7:0] WD_RST 28B4[7] WF_DIO4 28B1[2] WF_DIO52 28B1[1] WF_DIO55 28B1[0] WF_TMR 28B1[5] 28B1[3] WF_PB WF_RX 28B1[4] WF_CSTART 28B0[7] WF_RST 28B0[6] 28B0[5] WF_RSTBIT WF_OVF 28B0[4] WF_ERST 28B0[3] WF_BADVDD 28B0[2] 124 Rst Wk Dir Description This word describes the source of power and the status of the VDD ...
Page 125
... V rms is desired at the meter input, the digital value that should be programmed into SAG_THR (CE RAM 0x24) would be 80 Vrms * SQRT(2)/SAG_THR description of SAG_THR (see Table Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 77. Standard CE Codes Local Sensors Remote Sensor CE41A01 (Eq CE41A01 (Eq ...
Page 126
... Data Sheet The parameters EQU[2:0] (I/O RAM 0x2106[7:5]), CE_E (I/O RAM 0x2106[0]), and SUM_SAMPS[12:0] are essential to the function of the CE are stored in I/O RAM (see details). 5.3.4 Environment Before starting the CE using the CE_E bit (I/O RAM 0x2106[0]), the MPU has to establish the proper environment for the CE by implementing the following steps: • ...
Page 127
... CESTATUS provides information about the status of voltage and input AC signal frequency, which are useful for generating an early power fail warning to initiate necessary data storage. CESTATUS represents the Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet shows the MUX_SEL handles for the various sensor input pins. For on page 12), and the samples corresponding to this remote ...
Page 128
... CE Name Address 0x0030DB00 0x20 CECONFIG 0x00B0DB00 1. Default for CE41A01 (71M6541D/F/G or CE41A04 (71M6542F/G) CE code for use with local sensors. 2. Default for CE41B016201 and CE41B016601 codes that support the 71M6x01 remote sensors. Table 83: CECONFIG (CE RAM 0x20) Bit Definitions CECONFIG Name Default Description ...
Page 129
... APULSEW and APULSER (CE RAM 0x45 and 0x49). By setting EXT_PULSE = 0, the CE controls the pulse rate based on WSUM_X (CE RAM 0x84) and VARSUM_X (CE RAM 0x88). The 71M6541D/F/G and 71M6542F/G Demo Code creep function halts both internal and external pulse generation. Table 84: Sag Threshold and Gain Adjust Control ...
Page 130
... Data Sheet When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer variables. CE transfer variables are modified during the CE code pass that ends with an XFER_BUSY interrupt. They remain constant throughout each accumulation interval. In this data sheet, the names of CE transfer variables always end with “ ...
Page 131
... MAINEDGE_X (CE RAM 0x83) reflects the number of half-cycles accounted for in the last accumulated interval for the AC signal of the phase specified in the FREQSEL[1:0] field in CECONFIG (CE RAM 0x20[7:6]). MAINEDGE_X is useful for implementing a real-time clock based on the input AC signal. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 87) are the sum of the squared current and voltage samples Description ...
Page 132
... Data Sheet CE Name Address 0x82 FREQ_X 0x83 MAINEDGE_X 5.3.9 Pulse Generation Table 90 describes the CE pulse generation parameters. The combination of the CECONFIG PULSE_SLOW and PULSE_FAST bits (CE RAM 0x20[0:1]) controls the speed of the pulse rate. The default values of 0 and 0 maintain the original pulse rate given by the Kh equation ...
Page 133
... WPULSE_CTR 0x47 WPULSE_FRAC 0x48 WSUM_ACCUM 0x49 APULSER 0x4A VPULSE_CTR 0x4B VPULSE_FRAC 0x4C VSUM_ACCUM Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Description VMAX = Kh WRATE where 66.1782 (Local Sensors) 547 K = 109.1587 (Remote Sensor SUM_SAMPS[12:0] (CE RAM 0x23) ACC See Table 83 for the definition of X. ...
Page 134
... Data Sheet 5.3.10 Other CE Parameters Table 91 shows the CE parameters used for suppression of noise due to scaling and truncation effects. Table 91: CE Parameters for Noise Suppression and Code Version CE Name Default Address 0x25 QUANT_VA 0x26 QUANT_IA 0x27 QUANT_A 0x28 QUANT_VARA † ...
Page 135
... DLYADJ_A 0 0x15 DLYADJ_B 0 Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 92: CE Calibration Parameters Description These constants control the gain of their respective channels. The nominal value for each parameter is 2 channel is directly proportional to its CAL parameter. Thus, if the gain of a channel is 1% slow, CAL should be increased by 1%. ...
Page 136
... Data Sheet 5.3.12 CE Flow Diagrams Figure 44 through Figure 46 show the data flow through the CE in simplified form. Functions not shown include delay compensation, sag detection, scaling and the processing of meter equations. Figure 44: CE Data Flow: Multiplexer and ADC Figure 45: CE Data Flow: Scaling, Gain Control, Intermediate Variables ...
Page 137
... W0 W1 VAR0 VAR1 SQUARE Figure 46: CE Data Flow: Squaring and Summation Stages Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet SUM Σ Σ Σ Σ SUM_SAMPS=2520 SUM I0SQ Σ V0SQ Σ 2 I1SQ Σ MPU W0SUM_X W1SUM_X VAR0SUM_X VAR1SUM_X I0SQSUM_X ...
Page 138
... Data Sheet 6 Electrical Specifications This section provides the electrical specifications for the 71M654x. Please refer to the 71M6xxx Data Sheet for the 71M6x01 electrical specifications, pin-out, and package mechanical data. The devices are 100% production tested at room temperature, and performance over the full temperature range is guaranteed by design ...
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... V3P3SYS < 2.0 V Operating Temperature Notes: 1. GNDA and GNDD must be connected together. 2. V3P3SYS and V3P3A must be connected together. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Function Bypass capacitor for 3.3 V supply Bypass capacitor for 3.3 V output Bypass capacitor for V3P3SYS Bypass capacitor for VDD ...
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... Data Sheet 6.4 Performance Specifications 6.4.1 Input Logic Levels Parameter 1 Digital high-level input voltage 1 Digital low-level input voltage , V Input pullup current E_RXTX, E_RST, E_TCLK OPT_RX, OPT_TX SPI_CSZ (SEGDIO36) Other digital inputs Input pull down current ICE_E, RESET, TEST ...
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... Notes: 1. Guaranteed by design; not production tested. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Condition Min ���� = 3.3�� ������������ − 142 ) ∙ 0.0246�� + ���������� ∙ 297���� ...
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... Data Sheet 6.4.5 Supply Current The supply currents provided in Refer to the 71M6xxx Data Sheet for additional current required when using a 71M6x01 remote sensor. Table 100: Supply Current Performance Specifications Parameter I1: V3P3A + V3P3SYS current, Half-Speed (ADC_DIV=1) (see note 1) I1a: V3P3A + V3P3SYS current, ...
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... Threshold - Falling Threshold) 3.0 V Comparator 2.8 V Comparator 2.25 V Comparator 2.0 V Comparator 6.4.8 2.5 V Voltage Regulator – System Power Table 103: 2.5 V Voltage Regulator Performance Specifications Parameter V2P5 V2P5 load regulation Voltage overhead V3P3SYS-V2P5 Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Condition Min | ≤ V3P3D | ≤ V3P3D VBAT>2.5V V3P3SYS = 3V 10 V3P3D = 2 ...
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... Data Sheet 6.4.9 2.5 V Voltage Regulator – Battery Power Unless otherwise specified, V3P3SYS = V3P3A = 0, PB=GND (BRN). Table 104: Low-Power Voltage Regulator Performance Specifications Parameter V2P5 V2P5 load regulation Voltage Overhead 2V − VBAT-VDD 6.4.10 Crystal Oscillator Measurement conditions: Crystal disconnected, test load of 200 pF/100 kΩ between XOUT and GNDD. ...
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... Notes Notes: 1. These specifications apply to all COM and SEG pins. 2. VLCD = 2 LCD_VMODE=3, LCD_ON=1, LCD_BLANK=0, LCD_MODE=6, LCD_CLK=2. 4. Output load per SEG and COM pin. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet MIN CONDITION TYP MAX UNIT 145 ...
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... Data Sheet 6.4.13 VLCD Generator Table 108: LCD Driver Performance Specifications Parameter VSYS to VLCD switch impedance VBAT to VLCD switch impedance LCD Boost Frequency VLCD IOH current (VLCD(0)-VLCD(IOH)<0.25) ������������ ( ������_������ 5���� �������������0 + From LCDADJ0 and LCDADJ12 fuses: ( � ...
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... The following test conditions also apply to all parameters provided in this table: bypass capacitor CVLCD ≥ 1. 0.1 µF, test load RVLCD = 500 kΩ, no display, all SEGDIO pins configured as DIO. 2. Guaranteed by design; not production tested. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Condition LCD_VMODE[1: LCD_DAC[4: LCD_CLK[1:0]=2, LCD_MODE[2:0]=6 ...
Page 148
... Data Sheet 6.4.14 VREF Table 109 shows the performance specifications for the ADC reference voltage (VREF). Table 109: VREF Performance Specifications Parameter VREF output voltage, VREF(22) VREF output voltage, VREF(22) VREF output impedance VREF power supply sensitivity ΔVREF / ΔV3P3A ...
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... Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Condition Vin = 200 mV peak, 65 Hz, on VADC10 (VA VADC9 (VB)† †71M6542F/G only. Vcrosstalk = largest measurement on IAP-IAN or IBP-IBN Vin=65 Hz Vin=200 mV pk V3P3A=3.0 V, 3.6 V DIFF0_E=1, PRE_E=0 DIFF0_E=0, PRE_E 65Hz, 250mVpk, ...
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... Data Sheet Notes: 1. Guaranteed by design; not production tested. 2. Unless stated otherwise, the following test conditions apply to all the parameters provided in this table: FIR_LEN[1:0]=1, VREF_DIS=0, PLL_FAST=1, ADC_DIV=0, MUX_DIV=6, LSB values do not include the 9-bit left shift at CE input. 6.4.16 Pre-Amplifier for IAP-IAN ...
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... SPI Clock Low SPI Clock Freq SPI Freq/MPU Freq SPI Transaction Space SPI_CSZ rise to SPI_CSZ fall 6.5.3 EEPROM Interface Parameter 2 Write Clock frequency (I C) Write Clock frequency (3-wire) Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Condition -40 °C to +85 °C 25 °C 85 °C Condition Min ...
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... Data Sheet 6.5.4 RESET Pin Parameter Reset pulse width Reset pulse fall time (see note 1) Notes: 1. Guaranteed by design; not production tested. 6.5.5 RTC Parameter Range for date 152 Table 115: RESET Pin Timing Condition Table 116: RTC Range for Date ...
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... Package Outline Drawings 6.6.1 64-Pin LQFP Outline Package Drawing 11.7 12.3 PIN No. 1 Indicator 0.60 Typ. Figure 47: 64-pin LQFP Package Outline Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet 11.7 12.3 9.8 10.2 0.14 0.50 Typ. 0.28 0.00 0.20 1.40 1.60 153 ...
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... Data Sheet 6.6.2 100-Pin LQFP Package Outline Drawing Controlling dimensions are in mm. 1 14.000 +/- 0.200 0.225 +/- 0.045 Figure 48: 100-pin LQFP Package Outline 154 15.7(0.618) 16.3(0.641) Top View MAX. 1.600 1.50 +/- 0.10 0.50 TYP. 0.10 +/- 0.10 Side View 0.60 TYP> Rev 2 ...
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... Package markings comprise three lines of text and are as described in Line No. Markings 1 71M6541D- 2 IGT.428AB 3 104224TH Line No. Markings 1 71M6542G-IGT 2 110124TK 3 Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet ...
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... SPI_CSZ/SEGDIO36 3 4 COM0 5 COM1 6 COM2 7 COM3 8 SEGDIO27/COM4 SEGDIO26/COM5 9 SEGDIO25 10 11 SEGDIO24 12 SEGDIO23 13 SEGDIO22 14 SEGDIO21 15 SEGDIO20 16 SEGDIO19 Figure 50: Pinout for the 71M6541D/F/G (LQFP-64 Package) 156 Teridian 42 41 71M6541D 40 71M6541F XIN VBAT_RTC VBAT V3P3SYS IBP IBN GNDD ...
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... COM1 13 COM2 14 COM3 15 SEGDIO27/COM4 16 SEGDIO26/COM5 17 SEGDIO25 18 SEGDIO24 19 SEGDIO23 20 SEGDIO22 21 SEGDIO21 22 SEGDIO20 23 SEGDIO19 24 SEGDIO18 25 Figure 51: Pinout for the 71M6542F/G (LQFP-100 Package) Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Teridian 71M6542F XIN GNDA 72 VBAT_RTC 71 VBAT 70 V3P3SYS 69 IBP 68 67 IBN ...
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... Data Sheet 6.9 Pin Descriptions 6.9.1 Power and Ground Pins Pin types Power Output Input, I/O = Input/Output. The circuit number denotes the equivalent circuit, as specified under . Pin Pin Name (64 pin) (100-pin) 50 GNDA 72 GNDD V3P3A 45 69 V3P3SYS 41 V3P3D VDD ...
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... XOUT † Pin VB only available on 71M6542F/G. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 120: Analog Pins Differential or single-ended Line Current Sense Inputs: These pins are voltage inputs to the internal A/D converter. Typically, they are connected to the outputs of current sensors. Unused pins must be tied to V3P3A ...
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... Data Sheet 6.9.3 Digital Pins Table 121 lists the digital pins. Pin types Power Output Input, I/O = Input/Output, N connect. The circuit number denotes the equivalent circuit, as specified in Pin Pin Name (64-pin) (100-pin) 4-7 12–15 COM0–COM3 SEGDIO0/WPULSE SEGDIO1/VPULSE 29 43 ...
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... NC 66, 73, 74, 77, 78, 79, 84 Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Type Circuit ICE Enable. When zero, E_RST, E_TCLK, and E_RXTX become SEG50, SEG49, and SEG48 respectively. For I 2 production units, this pin should be pulled to GND to disable the emulator port. ...
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... Data Sheet 6.9.4 I/O Equivalent Circuits V3P3D V3P3D 110K Digital CMOS Input Input Pin GNDD Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D Digital CMOS Input Input Pin 110K GNDD GNDD Digital Input ...
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... Demo Board User’s Manual • 71M654x Software User’s Guide 9 Contact Information For more information about Maxim products or to check the availability of the 71M6541D/F/G and 71M6542F/G, contact technical support at www.maxim-ic.com/support. Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet Table 122. Ordering Information ...
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... Data Sheet Appendix A: Acronyms AFE Analog Front End AMR Automatic Meter Reading ANSI American National Standards Institute CE Compute Engine DIO Digital I /O DSP Digital Signal Processor FIR Finite Impulse Response Inter-IC Bus ICE In-Circuit Emulator IEC International Electrotechnical Commission ...
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... Added references to 71M6541G/2G throughout the document, as appropriate. 2 11/11 Added missing data sheet title header to odd and even pages. Corrected errata detected since the previous v1.1 (see indicated pages changed). Added section Rev 2 71M6541D/F/G and 71M6542F/G Data Sheet DESCRIPTION (Table 6.7 on page 155. PAGES CHANGED — ...
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... Data Sheet Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time ...