71M6541D Maxim, 71M6541D Datasheet - Page 79

• Manufacturer Part Number: 71M6541D
• Description: The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are Teridian™ 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core, low-power RTC with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

The TMUXOUT and TMUX2OUT pins may be used for diagnostics purposes during the product
development cycle or in the production test. The RTC 1-second output may be used to calibrate the
crystal oscillator. The RTC 4-second output provides higher precision for RTC calibration. RTCLK may
also be used to calibrate the RTC.
Rev 2
Note:
All
Note:
All
TMUX2[4:0]
TMUX[5:0]
TMUX2[4:0]
TMUX[5:0]
1C
1D
1B
1F
12
13
14
15
16
17
18
1F
A
D
E
C
1
9
A
B
E
0
1
2
3
8
9
values which are not shown are reserved.
values which are not shown are reserved.
Signal Name
RTCLK
WD_RST
CKMPU
V3AOK bit
V3OK bit
MUX_SYNC
CE_BUSY interrupt
CE_XFER interrupt
RTM output from CE
Signal Name
WD_OVF
PULSE_1S
PULSE_4S
RTCLK
SPARE[1] bit – I/O RAM
0x2704[1]
SPARE[2] bit – I/O RAM
0x2704[2]
WAKE
MUX_SYNC
MCK
GNDD
INT0 – DIG I/O
INT1 – DIG I/O
INT2 – CE_PULSE
INT3 – CE_BUSY
INT4 - VSTAT
INT5 – EEPROM/SPI
INT6 – XFER, RTC
RTM_CK (flash)
Table 66: TMUX2[4:0] Selections
Table 65: TMUX[5:0] Selections
Description
Indicates when the watchdog timer has expired (overflowed).
One second pulse with 25% Duty Cycle. This signal can be used
to measure the deviation of the RTC from an ideal 1 second
interval. Multiple cycles should be averaged together to filter out
jitter.
Four second pulse with 25% Duty Cycle. This signal can be used
to measure the deviation of the RTC from an ideal 4 second
interval. Multiple cycles should be averaged together to filter out
jitter. The 4 second pulse provides a more precise measurement
than the 1 second pulse.
32.768 kHz clock waveform
Copies the value of the bit stored in 0x2704[1]. For general
purpose use.
Copies the value of the bit stored in 0x2704[2]. For general
purpose use.
Indicates when a WAKE event has occurred.
Internal multiplexer frame SYNC signal. See Figure
7.
See
Digital GND. Use this signal to make the TMUX2OUT pin static.
Interrupt 0. See
See
Description
32.768 kHz clock waveform
Indicates when the MPU has reset the watchdog timer. Can be
monitored to determine spare time in the watchdog timer.
MPU clock – see
Indicates that the V3P3A pin voltage is ≥ 3.0 V. The V3P3A and
V3P3SYS pins are expected to be tied together at the PCB level.
The 71M654x monitors the V3P3A pin voltage only.
Indicates that the V3P3A pin voltage is ≥ 2.8 V. The V3P3A and
V3P3SYS pins are expected to be tied together at the PCB level.
The 71M654x monitors the V3P3A pin voltage only.
Internal multiplexer frame SYNC signal. See
7.
See
See
2.5.3
2.3.5
2.3.3
2.3.5
on page
on page 25.
on page
on page
2.4.8
Table 9
71M6541D/F/G and 71M6542F/G Data Sheet
50
25
25
on page 40. Also see
and
Figure 16
on page
Figure 16
Figure 6
47
6
and
on page 47.
and
Figure
Figure
79