71M6541D Maxim, 71M6541D Datasheet - Page 76

• Manufacturer Part Number: 71M6541D
• Description: The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are Teridian™ 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core, low-power RTC with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

71M6541D/F/G and 71M6542F/G Data Sheet
76
Name
EX_SPI
SPI_CMD
SPI_E
IE_SPI
SPI_SAFE
SPI_STAT
SFR FD[7:0]
SFR F8[7]
Location
2708[7:0]
270C[4]
270C[3]
2701[7]
Rst
0
–
1
0
0
0
Wk
0
–
1
0
0
0
Table 64: SPI Registers
R/W SPI interrupt enable bit.
R/W
R/W SPI interrupt flag. Set by hardware, cleared by writing a 0.
R/W
Dir
R
R
Description
SPI command. The 8-bit command from the bus master.
SPI port enable bit. It enables the SPI interface on pins
SEGDIO36 – SEGDIO39.
Limits SPI writes to SPI_CMD and a 16 byte region in
DRAM when set. No other write operations are permitted.
SPI_STAT contains the status results from the previous
SPI transaction.
Bit 7: Ready error: The 71M654x was not ready to read
or write as directed by the previous command.
Bit 6: Read data parity: This bit is the parity of all bytes
read from the 71M654x in the previous command. Does
not include the SPI_STAT byte.
Bit 5: Write data parity: This bit is the overall parity of the
bytes written to the 71M654x in the previous command.
It includes CMD and ADDR bytes.
Bit 4-2: Bottom 3 bits of the byte count. Does not include
ADDR and CMD bytes. One, two, and three byte
instructions return 111.
Bit 1: SPI FLASH mode: This bit is zero when the TEST
pin is zero.
Bit 0: SPI FLASH mode ready: Used in SPI FLASH
mode. Indicates that the flash is ready to receive
another write instruction.
Rev 2