71M6541D Maxim, 71M6541D Datasheet - Page 161

• Manufacturer Part Number: 71M6541D
• Description: The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are Teridian™ 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core, low-power RTC with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

(64-pin)
Pin
39
60
61
59
35
34
51
58
--
Rev 2
(100-pin)
26, 40,
48, 49,
50, 63,
64, 65,
66, 73,
74, 77,
78, 79,
Pin
59
92
93
91
55
54
81
90
84
TMUX2OUT/SEG46
TMUXOUT/SEG47
RESET
ICE_E
Name
TEST
NC
RX
PB
TX
Type
N/C
O
O
I
I
I
I
I
Circuit
4, 5
—
2
2
3
4
7
3
ICE Enable. When zero, E_RST, E_TCLK, and E_RXTX
become SEG50, SEG49, and SEG48 respectively. For
production units, this pin should be pulled to GND to disable
the emulator port.
Multiple-Use Pins. Configurable as either multiplexer/clock
output or LCD segment driver using the I/O RAM registers.
Chip Reset. This input pin is used to reset the chip into a
known state. For normal operation, this pin is pulled low. To
reset the chip, this pin should be pulled high. This pin has
an internal 30 μA (nominal) current source pulldown. No
external reset circuitry is necessary.
UART0 Input. If this pin is unused it must be terminated
to V3P3D or GNDD.
UART0 Output
Enables Production Test. This pin must be grounded in
normal operation.
Pushbutton Input. This pin must be at GNDD when not active
or unused. A rising edge sets the WF_PB flag. It also
causes the part to wake up if it is in SLP or LCD mode. PB
does not have an internal pullup or pulldown resistor.
No Connection. Do not connect this pin.
71M6541D/F/G and 71M6542F/G Data Sheet
Function
161