LMH1983SQE/NOPB National Semiconductor, LMH1983SQE/NOPB Datasheet - Page 21

• Manufacturer Part Number: LMH1983SQE/NOPB
• Description: IC VID CLK GEN MULTI RATE 40LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1983SQE/NOPB

• Applications: Video Equipment
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Interface Type: I2C
• Supply Voltage (max): 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH1983SQETR

ADD
0x47
0x48
0x49
0x4A
0x4B
to
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
Name
TOF3 Advanced
Control
Frame Reset MSB
TOF3 Advanced
Control
Frame Reset LSB
TOF4 Advanced
Control
AFS
TOF4 Advanced
Control
ACLK
Reserved
User Auto Format
27M High Value MSB
User Auto Format
27M High Value LSB
User Auto Format
27M Low Value MSB
User Auto Format
27M Low Value LSB
User Auto Format
R divider MSB
User Auto Format
R Divider LSB
User Auto Format
N Divider MSB
User Auto Format
N Divider LSB
User Auto Format
Charge Pump Current
User Auto Format
LPF MSB
User Auto Format
LPF LSB
User Auto Format
AFS
Bits
7:5
4:0
7:0
7:0
7:4
3:0
7:0
7:0
7:0
7:0
7:0
7:2
1:0
7:0
7
6:0
7:0
7:0
7:5
4:0
7:0
7:0
Field
RSVD
TOF3_RST_MSB
TOF3_RST_LSB
TOF4_AFS
RSVD
TOF4_ACLK
RSVD
USR_27M_High_M
SB
USR_27M_High_LS
B
USR_27M_Low_MS
B
USR_27M_Low_LS
B
RSVD
USR_DIV_R1_MSB
USR_DIV_R1_LSB
RSVD
USR_DIV_N1_MSB
USR_DIV_N1_LSB
USR_ICP
RSVD
USR_TOF_LPF_M
SB
USR_TOF_LPF_M
SB
USR_TOF4
21
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Default
00000
0x01
0x05
1011
0x00
0x00
0x00
0x00
00
0x00
0000000 See Applications Information section for
0x00
0x00
00000
0x00
0x00
Description
Reserved
Automatically loaded based on formats
selected.
See Applications Information section for
details. See also PLL4 Block Diagram.
Reserved
See Applications Information section for
details. See also PLL4 Block Diagram.
Reserved
User format detect is determined by looking
at the frequency of the Hsync input. This
frequency is measured by counting the
number of 27 MHz clock cycles that occur in
20 Hsync periods. This 16 bit register lists the
maximum number of 27 MHz clock cycles in
20 Hsync periods that could be considered to
meet the criteria for the User Format
User format detect is determined by looking
at the frequency of the Hysnc input. This
frequency is measured by counting the
number of 27 MHz clock cycles that occur in
20 Hsync periods. This 16 bit register lists the
minimum number of 27 MHz clock cycles in
20 Hsync periods that could be considered to
meet the criteria for the User Format
Reserved
See Applications Information section for
details.
See Applications Information section for
details.
Reserved
details.
See Applications Information section for
details.
See Applications Information section for
details.
Reserved
See Applications Information section for
details.
See Applications Information section for
details.
See Applications Information section for
details.
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