STV2050A STMicroelectronics, STV2050A Datasheet - Page 13

• Manufacturer Part Number: STV2050A
• Description: IC DGTL CONVERGENCE PROC 80-PQFP
• Manufacturer: STMicroelectronics
• Type: Videor

Specifications of STV2050A

• Applications: HDTV
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STV2050A - STRUCTURE OF THE PROGRAMMING SYSTEM
2.2 OVERVIEW OF EMBEDDED RAM ORGANIZATION
The RAM consists of 3 banks:
The first one, the “Red and I²C Bank”, uses 24-bit words. The two other banks, the “Green
Bank” and “Blue Bank”, both use 22-bit words. Each bank has 208 words with addresses from
00(hex) to CF(hex).
These 3 x 208 words are allocated to the “dynamic” convergence parameters. (Refer to
Sec-
tion 4.1 "CONVERGENCE CORRECTION VALUES" on page
18.)
The “Red and I²C Bank” has 33 additional words: addresses from D0(hex) to EF(hex) and
FE(hex). These words are used to buffer the I²C Bus registers.
As shown in this figure, each word can be pointed to by a sub-address (SA). Thus, each sub-
address points to 24- (or 22-, depending on the bank) bit wide words. A word virtually consists
of three bytes (24-bits) named D0, D1 and D2 as shown in the following figure. The bit order
is named as follows: D0[7] is the MSB and D2[0] is the LSB
MSB
LSB
D0 Byte
D1 Byte
D2 Byte
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Note: Bit D0[7:6] is not physically implemented in the “Green” and “Blue” banks.
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