STV2050A STMicroelectronics, STV2050A Datasheet - Page 48

• Manufacturer Part Number: STV2050A
• Description: IC DGTL CONVERGENCE PROC 80-PQFP
• Manufacturer: STMicroelectronics
• Type: Videor

Specifications of STV2050A

• Applications: HDTV
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STV2050A - CONVERGENCE
9.4 CALIBRATION
Calibrations can be carried out during manufacturing, or during the normal TV operating mode
using the automatic self-alignment procedure via the electrical loop. Refer to
"ELECTRICAL LOOP" on page
9.5 INTERPOLATION
The 10-bit dynamic correction values are expanded by interpolation to 14 precision bits.
The interpolation of the correction values stored in the embedded RAM produces correction
values for the lines between the grid lines.
9.5.1 Vertical Filter
A vertical interpolation is performed by the STV2050A in order to provide a smooth correction
transition between the stored points. A complex algorithm is implemented in order to improve
the interline geometrical aspect, even when not aligned during chassis production or by the
end user.
9.5.2 Horizontal Filter
For each of the three convergence correction channels, an interpolation filter is implemented
to calculate the correction values between horizontally-adjacent correction values. Different
configuration options are programmable using the D8 register.
The positions of the calculated additional correction values are timed independently for the
visible grid and the retrace grids.
Since operating the filters will increase the DAC frequency by a factor of 2 and 4 respectively,
it may be necessary to switch off the filters during the horizontal retrace if the retrace time is
short and the line frequency is high. In this case, the filter input data, coming from the vertical
interpolation, will be fed directly to the convergence DACs. In any case, this data is processed
by the filters in parallel to avoid any discontinuity when the filters are switched back into the
data paths.
9.6 NORMAL TV OPERATION MODE
The following bits must remain at logical “1” in the E3 register as defined by the default values
during reset:
– the CDO bit (refer to
48/83
HIF[1:0]
FSO
Section 9.8 "CONVERGENCE OUTPUTS" on page
00: Filter is not active
11: Filter is not active
01: Filter is a 3-tap FIR filter (2 values per grid)
10: Filter is a 5-tap FIR filter (4 values per grid)
0: Filter is switched off during horizontal retrace
1: Filter is running continuously
55.
51),
Section 11