IC SCHMT TRIG BUFF/DVR DL SC88-6

74LVC2G17GW,125

Manufacturer Part Number74LVC2G17GW,125
DescriptionIC SCHMT TRIG BUFF/DVR DL SC88-6
ManufacturerNXP Semiconductors
Series74LVC
74LVC2G17GW,125 datasheet
 

Specifications of 74LVC2G17GW,125

Package / CaseSC-70-6, SC-88, SOT-363Logic TypeSchmitt Trigger - Buffer, Driver
Number Of Elements2Number Of Bits Per Element1
Current - Output High, Low32mA, 32mAVoltage - Supply1.65 V ~ 5.5 V
Operating Temperature-40°C ~ 125°CMounting TypeSurface Mount
Logic FamilyLVCNumber Of Channels Per Chip2
PolarityNon-InvertingSupply Voltage (max)5.5 V
Supply Voltage (min)1.65 VMaximum Operating Temperature+ 125 C
Mounting StyleSMD/SMTHigh Level Output Current- 32 mA
Input Bias Current (max)40 uALow Level Output Current32 mA
Minimum Operating Temperature- 40 CPropagation Delay Time3.8 ns (Typ) @ 2.7 V or 3.6 ns (Typ) @ 3.3 V or 2.7 ns (Typ) @ 5 V
Number Of Lines (input / Output)2 / 2Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other names568-4841-2
74LVC2G17GW,125
74LVC2G17GW-G
74LVC2G17GW-G
935273321125
  
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74LVC2G17
Dual non-inverting Schmitt trigger with 5 V tolerant input
Rev. 5 — 6 August 2010
1. General description
The 74LVC2G17 provides two non-inverting buffers with Schmitt trigger action. It is
capable of transforming slowly changing input signals into sharply defined, jitter-free
output signals.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
The I
OFF
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD-8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
±24 mA output drive (V
CMOS low-power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Applications
Wave and pulse shapers for highly noisy environments
circuitry disables the output, preventing the damaging backflow current through
= 3.0 V)
CC
Product data sheet
.
OFF

74LVC2G17GW,125 Summary of contents

  • Page 1

    Dual non-inverting Schmitt trigger with 5 V tolerant input Rev. 5 — 6 August 2010 1. General description The 74LVC2G17 provides two non-inverting buffers with Schmitt trigger action capable of transforming slowly changing input signals into sharply ...

  • Page 2

    ... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range −40 °C to +125 °C 74LVC2G17GW −40 °C to +125 °C 74LVC2G17GV −40 °C to +125 °C 74LVC2G17GM −40 °C to +125 °C 74LVC2G17GF −40 °C to +125 °C 74LVC2G17GN −40 °C to +125 °C 74LVC2G17GS 5 ...

  • Page 3

    ... NXP Semiconductors Fig 3. Logic diagram 7. Pinning information 7.1 Pinning 74LVC2G17 GND 001aaf078 Fig 4. Pin configuration SOT363 and SOT457 7.2 Pin description Table 3. Pin description Symbol Pin 1A 1 GND Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level. 74LVC2G17 ...

  • Page 4

    ... NXP Semiconductors 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...

  • Page 5

    ... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output voltage OH I input leakage current I I power-off leakage current OFF I supply current CC ΔI additional supply current CC C input capacitance I = −40 °C to +125 °C ...

  • Page 6

    ... NXP Semiconductors 12. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t propagation delay nA to nY; see power dissipation per buffer capacitance V I [1] Typical values are measured the same as t and PLH PHL ...

  • Page 7

    ... NXP Semiconductors Table 9. Measurement points Supply voltage 1. 2.7 V 2 3 5.5 V Measurement points are given in Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. ...

  • Page 8

    ... NXP Semiconductors 14. Transfer characteristics Table 11. Transfer characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V positive-going see T+ threshold voltage negative-going see T− threshold voltage hysteresis voltage ( Figure [1] All typical values are measured at T 15. Waveforms transfer characteristics T− ...

  • Page 9

    ... NXP Semiconductors Fig 11. Typical transfer characteristic (1) Positive-going edge (2) Negative-going edge Linear change of V between 0 2.0 V. All values given are typical unless otherwise specified. I Fig 12. Average function 74LVC2G17 Product data sheet Dual non-inverting Schmitt trigger with 5 V tolerant input (mA 0 (mA) ...

  • Page 10

    ... NXP Semiconductors 16. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 1.1 0.30 0.25 mm 0.1 0.8 0.20 0.10 OUTLINE VERSION IEC SOT363 Fig 13. Package outline SOT363 (SC-88) 74LVC2G17 Product data sheet Dual non-inverting Schmitt trigger with 5 V tolerant input ...

  • Page 11

    ... NXP Semiconductors Plastic surface-mounted package (TSOP6); 6 leads y 6 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) UNIT 0.1 1.1 0.40 0.26 mm 0.013 0.9 0.25 0.10 OUTLINE VERSION IEC SOT457 Fig 14. Package outline SOT457 (SC-74) 74LVC2G17 Product data sheet Dual non-inverting Schmitt trigger with 5 V tolerant input ...

  • Page 12

    ... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. 6× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

  • Page 13

    ... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 16 ...

  • Page 14

    ... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

  • Page 15

    ... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

  • Page 16

    ... NXP Semiconductors 17. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 18. Revision history Table 13. Revision history Document ID Release date 74LVC2G17 v.5 20100806 • Modifications: Added type number 74LVC2G17GN (SOT1115/XSON6 package). ...

  • Page 17

    ... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

  • Page 18

    ... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 20. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVC2G17 Product data sheet Dual non-inverting Schmitt trigger with 5 V tolerant input 19 ...

  • Page 19

    ... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Functional description . . . . . . . . . . . . . . . . . . . 3 9 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 13 Waveforms ...