74LVT244APW,118 NXP Semiconductors, 74LVT244APW,118 Datasheet

IC BUFF/DVR TRI-ST DUAL 20TSSOP

74LVT244APW,118

Manufacturer Part Number
74LVT244APW,118
Description
IC BUFF/DVR TRI-ST DUAL 20TSSOP
Manufacturer
NXP Semiconductors
Series
74LVTr
Datasheet

Specifications of 74LVT244APW,118

Package / Case
20-TSSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
4
Current - Output High, Low
32mA, 64mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Logic Family
LVT
Number Of Channels Per Chip
8
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
High Level Output Current
- 32 mA
Input Bias Current (max)
12000 uA
Low Level Output Current
32 mA
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Output Current
128 mA
Output Type
3-State
Output Voltage
7 V
Propagation Delay Time
2.6 ns (Typ) @ 3.3 V
Logical Function
Buffer/Line Driver
Number Of Elements
2
Number Of Channels
8
Number Of Inputs
8
Number Of Outputs
8
Operating Supply Voltage (typ)
3.3V
Package Type
TSSOP
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.7V
Quiescent Current
12mA
Technology
BiCMOS
Pin Count
20
Mounting
Surface Mount
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Number Of Lines (input / Output)
8 / 8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2316-2
74LVT244APW-T
935176380118
1. General description
2. Features
3. Ordering information
Table 1.
Type number
74LVT244AD
74LVTH244AD
74LVT244ADB
74LVTH244ADB
74LVT244APW
74LVTH244APW
74LVT244ABQ
74LVTH244ABQ
Ordering information
Package
Temperature range Name
40 C to +85 C
40 C to +85 C
40 C to +85 C
40 C to +85 C
The 74LVT244A; 74LVTH244A is a high-performance BiCMOS product designed for V
operation at 3.3 V.
This device is an octal buffer that is ideal for driving bus lines. The device features two
output enables (1OE, 2OE), each controlling four of the 3-state outputs.
I
I
I
I
I
I
I
I
I
I
I
74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
Rev. 04 — 3 September 2008
Octal bus interface
3-state buffers
Output capability: +64 mA and 32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection
ESD protection:
N
N
N
JESD78 Class II exceeds 500 mA
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
SO20
SSOP20
TSSOP20
DHVQFN20 plastic dual in-line compatible thermal enhanced
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
very thin quad flat package; no leads;
20 terminals; body 2.5
4.5
0.85 mm
Product data sheet
Version
SOT163-1
SOT339-1
SOT360-1
SOT764-1
CC

Related parts for 74LVT244APW,118

74LVT244APW,118 Summary of contents

Page 1

V octal buffer/line driver; 3-state Rev. 04 — 3 September 2008 1. General description The 74LVT244A; 74LVTH244A is a high-performance BiCMOS product designed for V operation at 3.3 V. This device is an octal buffer that is ...

Page 2

... NXP Semiconductors 4. Functional diagram 1A0 2 1A1 4 1A2 6 1A3 8 1OE 1 2A0 11 2A1 13 2A2 15 2A3 17 2OE 19 Fig 1. Logic symbol 74LVT_LVTH244A_4 Product data sheet 74LVT244A; 74LVTH244A 1Y0 18 1Y1 16 1Y2 14 1Y3 12 2Y0 9 2Y1 7 2Y2 5 2Y3 3 mna825 Fig 2. Rev. 04 — 3 September 2008 3.3 V octal buffer/line driver; 3-state ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74LVT244A 74LVTH244A 1OE 1 1A0 2 3 2Y3 4 1A1 2Y2 5 1A2 6 7 2Y1 1A3 8 2Y0 9 10 GND Fig 3. Pin configuration for SO20 and (T)SSOP20 5.2 Pin description Table 2. Pin description Symbol Pin 1OE, 2OE 1, 19 1A0, 1A1, 1A2, 1A3 ...

Page 4

... NXP Semiconductors 6. Functional description 6.1 Function table [1] Table 3. Function table Control nOE HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

Page 5

... NXP Semiconductors Table 5. Operating conditions Symbol Parameter I LOW-level output current OL T ambient temperature amb t/ V input transition rise and fall rate outputs enabled 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter [ +85 C amb ...

Page 6

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I OFF-state output current OZ I supply current CC I additional supply current CC C input capacitance I C output capacitance O [1] All typical values are amb [2] Unused pins GND. ...

Page 7

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter t LOW to OFF-state PLZ propagation delay [1] All typical values are 3.3 V and T CC 11. Waveforms Measurement points are given in V and V are typical voltage output levels that occur with the output load. ...

Page 8

... NXP Semiconductors Test data is given in Table Definitions test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Test voltage for switching times. EXT Fig 7. Load circuitry for switching times Table 9. Test data Input 2.7 V ...

Page 9

... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 9. ...

Page 11

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 12

... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 13

... Release date 74LVT_LVTH244A_4 20080903 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 3 “Ordering information” added. ...

Page 14

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 15

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Abbreviations ...

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