TB6572AFG*** Toshiba, TB6572AFG*** Datasheet - Page 15

• Manufacturer Part Number: TB6572AFG***
• Manufacturer: Toshiba

Specifications of TB6572AFG***

• Function: Controller
• Vopmax (vm*): 17V (30V)
• Io (lpeak): 20mA
• Sinusoidal Current Wave: yes
• Sensor-less: no
• Speed Feedback Loop: yes
• Package: QFP52
• Rohs Compatible†: yes

9. Hall Amplifier
10. Ready Circuit
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*: The internal system clock is generated by the on-chip PLL from an external clock. The system clock frequency
The Hall amplifier accepts Hall device output signals. If input signals contain noise, connect a capacitor
between inputs.
The common-mode input voltage range is: VCMRH = 0.5 to 3.4 V.
The Hall amplifier has an input hysteresis of ±16 mV (typ).
The Hall amplifier converts Hall device signals into square waves, which then enter the internal logic.
Outputs from the Hall amplifier are pulled up with resistors. If positive/negative inputs are open, the
output is recognized as high. If the Hall amplifier outputs are H: H: H or L: L: L, the energization
outputs are as follows:
LA (U) = LB (U) = LC (U) = L and LA (L) = LB (L) = LC (L) = L.
The Ready circuit indicates the motor rotation speed state using two states (L and HZ) of an
open-collector output.
When the motor is rotating, the circuit counts FG signals and outputs the following states according to
whether the frequency is within or outside ±6% of the specified value:
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory
purposes.
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Connect a pull-up resistor to the Ready output pin. Determine the resistance considering the following
characteristics. The input current is 2 mA (max).
may saturate, depending on the external LPF and VCO constants. The speed discriminator compares the
reference frequency derived from the system clock against the FG frequency. If the system clock frequency
saturates, the system clock is not synchronized to the FG signal. (Instead, the system clock is synchronized
with the reference frequency.) At this time, the READY signal remains Low. The LPF and VCO constants
should be optimized.
Within ±6% of motor rotation speed: L output
Outside ±6% of motor rotation speed: HZ (high impedance)
VCER = 0.5 V (max) at IR = 2 mA
V
ref1
V
ref1
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Ready
TB6572AFG
2008-1-21