N80C196KC-20 Intel Corporation, N80C196KC-20 Datasheet
N80C196KC-20
Available stocks
Related parts for N80C196KC-20
N80C196KC-20 Summary of contents
Page 1
Supplement to 8XC196Kx, 8XC196Jx, 87C196CA User’s Manual August 1998 Order Number: 272973-002 ...
Page 2
... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners. ...
Page 3
CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS ................................................................................................... 1-1 1.2 RELATED DOCUMENTS .............................................................................................. 1-2 CHAPTER 2 ARCHITECTURAL OVERVIEW 2.1 MICROCONTROLLER FEATURES .............................................................................. 2-1 2.2 BLOCK DIAGRAM......................................................................................................... 2-2 2.3 INTERNAL TIMING........................................................................................................ 2-2 2.4 EXTERNAL TIMING ...................................................................................................... 2-5 2.5 INTERNAL ...
Page 4
X SUPPLEMENT CHAPTER 6 SYNCHRONOUS SERIAL I/O PORT 6.1 SSIO 0 CLOCK REGISTER........................................................................................... 6-1 6.2 SSIO 1 CLOCK REGISTER........................................................................................... 6-2 CHAPTER 7 EVENT PROCESSOR ARRAY 7.1 EPA FUNCTIONAL OVERVIEW ................................................................................... 7-1 7.1.1 EPA Mask Registers .................................................................................................7-4 7.1.2 EPA Pending ...
Page 5
PROGRAMMING THE J1850 CONTROLLER ............................................................ 8-16 8.6.1 Programming the J1850 Command (J_CMD) Register ..........................................8-16 8.6.2 Programming the J1850 Configuration (J_CFG) Register ......................................8-18 8.6.3 Programming the J1850 Delay Compensation (J_DLY) Register ...........................8-19 8.6.4 Programming the J1850 Status (J_STAT) Register ................................................8-21 ...
Page 6
X SUPPLEMENT Figure 2-1 8XC196L x Block Diagram ............................................................................................2-2 2-2 Clock Circuitry (87C196LA, LB Only) ...........................................................................2-3 2-3 Internal Clock Phases (Assumes PLL is Bypassed).....................................................2-4 2-4 Effect of Clock Mode on Internal CLKOUT Frequency.................................................2-5 2-5 Unerasable PROM 1 (USFR1) Register ...
Page 7
Figure 11-1 Slave Programming Circuit.........................................................................................11-3 11-2 Serial Port Programming Circuit .................................................................................11-4 A-1 87C196LA 52-pin PLCC Package ............................................................................... A-3 A-2 87C196LB 52-pin PLCC Package ............................................................................... A-5 A-3 83C196LD 52-pin PLCC Package............................................................................... A-7 FIGURES CONTENTS Page vii ...
Page 8
X SUPPLEMENT Table 1-1 Related Documents ......................................................................................................1-2 2-1 Features of the 8XC196L x and 8XC196K x Product Famiies .......................................2-1 2-2 State Times at Various Frequencies ............................................................................2-4 2-3 Relationships Between Input Frequency, Clock Multiplier, and State Times ...............2-5 2-4 UPROM ...
Page 9
Guide to This Manual 1 ...
Page 10
...
Page 11
This document is a supplement to the 8XC196Kx, 8XC196Jx, 87C196CA Microcontroller Family User’s Manual. It describes the differences between the 8XC196Lx and the 8XC196Kx family of microcontrollers. For information not found in this supplement, please consult the 8XC196Kx, 8XC196Jx, 87C196CA ...
Page 12
X SUPPLEMENT Appendix A — Signal Descriptions — provides reference information for the 8XC196Lx de- vice pins, including descriptions of the pin functions, reset status of the I/O and control pins, and package pin assignments. Glossary — defines terms ...
Page 13
Architectural Overview 2 ...
Page 14
...
Page 15
This chapter describes architectural differences between the 8XC196Lx (87C196LA, 87C196LB, and 83C196LD) and the 8XC196Kx (8XC196Kx, 8XC196Jx, and 87C196CA) microcontroller families. Both the 8XC196Lx and the 8XC196Kx are designed for high-speed calculations and fast I/O, and share a common architecture ...
Page 16
X SUPPLEMENT 2.2 BLOCK DIAGRAM Figure 2 simplified block diagram that shows the major blocks within the microcontroller. Observe that the slave port peripheral does not exist on the 8XC196Lx. Core (CPU, Memory Controller) Clock and Power ...
Page 17
F XTAL1 XTAL1 XTAL2 Disable Oscillator (Powerdown) Figure 2-2. Clock Circuitry (87C196LA, LB Only) The rising edges of PH1 and PH2 generate the internal CLKOUT signal (Figure 2-3). The clock circuitry routes separate internal clock signals to the CPU and ...
Page 18
X SUPPLEMENT XTAL1 PH1 PH2 CLKOUT Phase 1 Figure 2-3. Internal Clock Phases (Assumes PLL is Bypassed) The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a ...
Page 19
XTAL1 (16 MHz) f PLLEN = 62.5ns Internal CLKOUT f PLLEN = 31.25ns Internal CLKOUT Figure 2-4. Effect of Clock Mode on Internal CLKOUT Frequency Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and ...
Page 20
X SUPPLEMENT USFR1 (read only) The UPROM special-function register 1 (USFR1) reflects the status of unerasable, programmable read-only memory (UPROM) locations. This read-only register reflects the status of two bits that control the output frequency on CLKOUT. 7 — ...
Page 21
I/O Ports The I/O ports of the 8XC196Lx are functionally identical to those of the 8XC196Jx. However, on the 87C196LA and LB the reset state level of all 41 general-purpose I/O pins has changed from a weak logic “1” ...
Page 22
...
Page 23
Address Space 3 ...
Page 24
...
Page 25
This chapter describes the differences in the address space of the 8XC196Lx from that of the 8XC196Kx. 3.1 ADDRESS PARTITIONS Table 3 address map of the 8XC196Lx and 8XC196Kx microcontroller family members. Device and Hex Address Range FFFF ...
Page 26
X SUPPLEMENT Table 3-1. Address Map (Continued) Device and Hex Address Range 1BFF 1BFF 1BFF — 0500 0500 0600 04FF 04FF — — 0400 0400 03FF 05FF — — 0200 0180 03FF 01FF 017F 02FF 0100 0100 0100 0100 ...
Page 27
Address 03FFH Upper Register File 0100H 00FFH Lower Register File 0000H Figure 3-1. Register File Address Map Table 3-2. Register File Memory Addresses Device and Hex Address Range JV CA,JT,KT LA, LB JR, KR 1DFF — — — 1C00 03FF ...
Page 28
X SUPPLEMENT 3.3 PERIPHERAL SPECIAL-FUNCTION REGISTERS Table 3-3 lists the peripheral SFR addresses. Highlighted addresses are unique to the 8XC196Lx. Table 3-3. 8XC196L x Peripheral SFRs Ports and UPROM SFRs Address High (Odd) Byte Low (Even) ...
Page 29
Table 3-3. 8XC196L x Peripheral SFRs (Continued) SIO and SSIO SFRs Address High (Odd) Byte Low (Even) Byte 1FBEH Reserved Reserved 1FBCH SP_BAUD (H) SP_BAUD (L) 1FBAH SP_CON SBUF_TX 1FB8H SP_STATUS SBUF_RX 1FB6H SSIO1_CLK Reserved 1FB4H SSIO0_CLK SSIO_BAUD 1FB2H SSIO1_CON ...
Page 30
X SUPPLEMENT 3.4 WINDOWING Windowing maps a segment of higher memory (the upper register file or peripheral SFRs) into the lower register file. The window selection register (WSR) selects a 32-, 64- or 128-byte seg- ment of higher memory ...
Page 31
Table 3-4. Windows (Continued) WSR Value Base for 32-byte Window Address (00E0–00FFH) Register RAM (87C196JV Only; Continued) 1CE0H 67H 1CC0H 66H 1CA0H 65H 1C80H 64H 1C60H 63H 1C40H 62H 1C20H 61H 1C00H 60H Upper Register File (CA, JT, JV, KT) ...
Page 32
X SUPPLEMENT Table 3-4. Windows (Continued) WSR Value Base for 32-byte Window Address (00E0–00FFH) Upper Register File (CA, JR, JT, JV, KR, KT, LA, LB, LD) 0160H 4BH 0140H 4AH 0120H 49H 0100H 48H NOTE: Locations 1FE0–1FFFH contain memory-mapped ...
Page 33
Standard and PTS Interrupts 4 ...
Page 34
...
Page 35
STANDARD AND PTS INTERRUPTS The interrupt structure of the 8XC196Lx is the same as that of the 8XC196Jx. The only difference is that the slave port interrupts (INT08:06) now support the J1850 controller peripheral. 4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIES ...
Page 36
X SUPPLEMENT Table 4-1. Interrupt Sources, Vectors, and Priorities Interrupt Source Mnemonic Nonmaskable Interrupt NMI EXTINT Pin EXTINT Reserved — SIO Receive RI SIO Transmit TI SSIO Channel 1 Transfer SSIO1 SSIO Channel 0 Transfer SSIO0 J1850 Status (LB ...
Page 37
Interrupt Mask Registers Figures 4-1 and 4-2 illustrate the interrupt mask registers for the 8XC196Lx microcontrollers. INT_MASK The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of ...
Page 38
X SUPPLEMENT INT_MASK1 The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can be read from or written ...
Page 39
INT_PEND When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding ...
Page 40
X SUPPLEMENT INT_PEND1 When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by ...
Page 41
PTSSEL The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit selects a standard interrupt service routine. In ...
Page 42
X SUPPLEMENT PTSSRV The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit and sets ...
Page 43
I/O Ports 5 ...
Page 44
...
Page 45
The I/O ports of the 8XC196Lx are functionally identical to those of the 8XC196Jx. However, on the 87C196LA and LB, the reset state level of all 41 general-purpose I/O pins has changed from a weak logic “1” (wk1 ...
Page 46
X SUPPLEMENT input signals set SFDIR. Even if a pin used in special-function mode, you must still ini- tialize the pin as an input or output by writing to the port direction register. Resistor R1 provides ...
Page 47
Internal Bus P x _REG SFDATA P x _DRV SFDIR P x _MODE Read Port RESET# Any Write _MODE Figure 5-1. Ports and 6 Internal Structure (87C196LA, LB Only) 5.2.1 Configuring Ports 1, 2, ...
Page 48
X SUPPLEMENT impedance input, or open-drain output. The port direction and data output registers select the con- figuration for each pin. Complementary output means that the microcontroller drives the signal high or low. High-impedance input means that the microcontroller ...
Page 49
Be certain that your system meets the V prevent inadvertent entry into ONCE mode or a test mode. 3. Following reset, P2.7/CLKOUT carries the strongly driven CLKOUT signal not held low. When P2.7/CLKOUT is ...
Page 50
X SUPPLEMENT Internal Bus P x _REG Address/Data Bus Control Select 0 = Address/Data 1 = I/O P34_DRV Read Port RESET# Figure 5-2. Ports 3 and 4 Internal Structure (87C196LA, LB Only) 5 RESET# Sample Latch P ...
Page 51
Synchronous Serial I/O Port 6 ...
Page 52
...
Page 53
SYNCHRONOUS SERIAL I/O PORT The synchronous serial I/O (SSIO) port on the 8XC196Lx has been enhanced, implementing two new special function registers (SSIO0_CLK and SSIO1_CLK) that allow you to select the oper- ating mode and configure the phase and polarity ...
Page 54
X SUPPLEMENT For transmissions, SSIO0_CLK determines whether the SSIO shifts out data bits on rising or fall- ing clock edges. For receptions, SSIO0_CLK determines whether the SSIO samples data bits on rising or falling clock edges. 6.2 SSIO 1 ...
Page 55
SSIO1_CLK (Continued) The SSIO 1 clock (SSIO1_CLK) register selects the SSIO mode of operation (standard, duplex, or channel-select), enables the channel-select master contention interrupt request, and selects the phase and polarity for the serial clock (SC1) for channel 1. 7 ...
Page 56
...
Page 57
Event Processor Array 7 ...
Page 58
...
Page 59
The EPA on the 8XC196Lx is functionally identical to that of the 8XC196Jx; however, the 8XC196Lx has only two capture/compare channels without pins instead of four. In addition, the 83C196LD has no compare-only channels. 7.1 EPA FUNCTIONAL OVERVIEW Table 7-1 ...
Page 60
X SUPPLEMENT Timer-Counter Unit TIMER1 TIMER2 EPA 3:0 EPA8 / COMP0 EPA9 / COMP1 Figure 7-1. EPA Block Diagram (87C196LA, LB Only) 7-2 Capture/Compare EPA 3:0 Interrupts Channel 0–3 Capture/Compare Channel 6–7 Capture/Compare Channel 8 Indirect Compare-only Interrupt Channel ...
Page 61
Timer-Counter Unit TIMER1 TIMER2 Capture/Compare Channel 0–3 EPA 3:0 Capture/Compare Channel 6–7 Capture/Compare EPA8 Channel 8 Capture/Compare Channel 9 EPA9 Figure 7-2. EPA Block Diagram (83C196LD Only) EVENT PROCESSOR ARRAY EPA 3:0 Interrupts EPA x Interrupt Indirect Interrupt Processor Logic ...
Page 62
X SUPPLEMENT 7.1.1 EPA Mask Registers Figures 7-3 and 7-4 illustrate the EPA mask registers, EPA_MASK and EPA_MASK1, for the 8XC196Lx microcontroller family. EPA_MASK The EPA interrupt mask (EPA_MASK) register enables or disables (masks) interrupts associated with the shared ...
Page 63
EPA Pending Registers Figures 7-5 and 7-6 illustrate the EPA pending registers, EPA_PEND and EPA_PEND1, for the 8XC196Lx microcontroller family. EPA_PEND When hardware detects a pending EPA6–9 or OVR0–3, 8–9 interrupt request, it sets the corresponding bit in the ...
Page 64
X SUPPLEMENT 7.1.3 EPA Interrupt Priority Vector Register Figure 7-7 illustrates the EPA interrupt priority vector (EPAIPV) register for the 8XC196Lx mi- crocontroller family. EPAIPV When an EPA x interrupt occurs, the EPA interrupt priority vector (EPAIPV) register contains ...
Page 65
J1850 Communications Controller 8 ...
Page 66
...
Page 67
J1850 COMMUNICATIONS CONTROLLER The J1850 communications controller manages communications between multiple network nodes. This integrated peripheral supports the 10.4 Kb/s VPW (variable pulse width) medium- speed class B in-vehicle network protocol. It also supports both the standard and in-frame re- ...
Page 68
X SUPPLEMENT The J1850 controller can handle network protocol functions including message frame sequenc- ing, bit arbitration, in-frame response (IFR) messaging, error detection, and delay compensation. The J1850 communications controller (Figure 8-2) consists of a control state machine (CSM), ...
Page 69
J1850 CONTROLLER SIGNALS AND REGISTERS Table 8-1 describes the J1850 controller’s pins, and Table 8-2 describes the control and status registers. Table 8-1. J1850 Controller Signals Signal Type RXJ1850 I Receive Carries digital symbols from a remote transceiver to ...
Page 70
X SUPPLEMENT Table 8-2. Control and Status Registers (Continued) Mnemonic Address INT_MASK 0008H Interrupt Mask INT_MASK1 0013H Interrupt Mask 1 INT_PEND 0009H Interrupt Pending INT_PEND1 0012H Interrupt Pending 1 PTSSEL 0004H PTS Select PTSSRV 0006H PTS Service 8.3 J1850 ...
Page 71
Bus Contention Bus contention arises when multiple nodes attempt to access and transmit message frames across the J1850 bus simultaneously. This creates a conflict on the bus. The recognition of conflicting symbols or bits on the bus is referred ...
Page 72
X SUPPLEMENT 8.3.2.1 Clock Prescaler Because the 87C196LB microcontroller can operate at a variety of input frequencies (F clock prescaler circuitry is used to provide a single, internal clock frequency (f/2) to ensure that the J1850 peripheral is clocked ...
Page 73
Figure 8-3. Huntzicker Symbol Definition for J1850 A symbol is defined as a timing-level formatted bit. The VPW symbol timing requirements stip- ulate that there is one symbol per transition and one ...
Page 74
X SUPPLEMENT of arbitration, nodes A, C, and D are all transmitting an “active 0” symbol, thus the idle state of the “passive 1” symbol is overruled in favor of the driven state of the “active 0” symbol. Node ...
Page 75
Standard Frame S 1-3 Bytes 1-11 Bytes O Header Data F In-frame Response (IFR) Frame S 1-3 Bytes 1-11 Bytes O Header Data F † The number of data bytes to be transferred is unspecified if 0EH is written to ...
Page 76
X SUPPLEMENT (J_CFG.7) and considers whether the IFR message response has a CRC byte appended. Figure 8-7 depicts the SAE preferred, active-level state bit format timing for the NB. 64µ for IFR without CRC Figure 8-7. ...
Page 77
Figure 8-8. Definition for Start and End of Frame Symbols Table 8-4 details the symbol timing characteristics supported by the 87C196LB. Table 8-4. Huntzicker Symbol Timing Characteristics Name Symbol Passive ...
Page 78
X SUPPLEMENT 8.4.2 In-frame Response Messaging There are three types of in-frame response (IFR) message framings: type 1 (a single byte from a single responder), type 2 (a single byte from multiple responders), and type 3 (multiple bytes from ...
Page 79
In-frame Response (IFR) Frame S 1-3 Bytes 1-11 Bytes O Header Data F † The number of data bytes to be transferred is unspecified if 0EH is written to J_CMD3:0. †† Each D block in the IFR data field represents ...
Page 80
X SUPPLEMENT J_TX The J1850 transmitter (J_TX) register transfers data in byte increments to the J1850 bus from the microcontroller CPU. This register is buffered to allow for transmission of a second data byte while the first data byte ...
Page 81
An overrun condition can occur on transmission if the transmit buffer, JTX_BUF, is overwritten. 8.5.2 Receiving Messages For a message reception, after a SOF is detected on the bus, the controller starts to shift data sym- bols into the J1850 ...
Page 82
X SUPPLEMENT If a third byte is received before J_RX is read, a J1850ST core interrupt is generated and the OVR_UNDR (J_STAT.3) bit records a receiver overrun error in the J_STAT register. 8.5.3 IFR Messages In-frame response (IFR) messaging ...
Page 83
J_CMD The J1850 command (J_CMD) register determines the messaging type, specifies the number of bytes to be transmitted in the next message frame, and updates the status of the message transmission in progress. This byte register can be directly addressed ...
Page 84
X SUPPLEMENT 8.6.2 Programming the J1850 Configuration (J_CFG) Register The J1850 configuration register (Figure 8-17) selects the proper oscillator prescaler, initiates a transmission break for debugging, invokes clock quadrupling operation, and selects the normal- ization bit format. J_CFG The ...
Page 85
J_CFG The J1850 configuration (J_CFG) register selects the proper oscilator prescaler, initiates transmission break for debug, invokes clock quadrupling operation, and selects the normalizartion bit format. This byte register can be directly addressed through windowing . All J1850 bus activity ...
Page 86
X SUPPLEMENT J_DLY The J1850 delay (J_DLY) register allows you compensate for the inherent propagation delays and to accurately resolve bus contention during arbitration. This byte register can be directly addressed through windowing . 7 — — — Bit ...
Page 87
Programming the J1850 Status (J_STAT) Register The J1850 status register (Figure 8-19) provides the current status of the message and the four interrupt sources associated with the J1850 protocol. J_STAT The J1850 status (J_STAT) register provides the current status ...
Page 88
X SUPPLEMENT J_STAT The J1850 status (J_STAT) register provides the current status of the message transfer, the receive and transmit buffers, and the four interrupt sources associated with the J1850 protocol. This byte register can be directly addressed through ...
Page 89
Minimum Hardware Considerations 9 ...
Page 90
...
Page 91
MINIMUM HARDWARE CONSIDERATIONS This chapter discusses the major hardware consideration differences between the 8XC196Lx and the 8XC196Kx. The 8XC196Lx has implemented a reset source SFR that reveals the source of the most recent reset request. 9.1 IDENTIFYING THE RESET SOURCE ...
Page 92
X SUPPLEMENT 9.2 DESIGN CONSIDERATIONS FOR 8XC196LA, LB, AND LD With the exception of a few new multiplexed functions, the 8XC196Lx microcontrollers are pin compatible with the 8XC196Jx microcontrollers. The 8XC196Jx microcontrollers are 52-lead versions of 8XC196Kx microcontrollers. Follow ...
Page 93
Special Operating Modes 10 ...
Page 94
...
Page 95
The 8XC196Lx’s idle and powerdown modes are the same as those of the 8XC196Kx. However, the clock circuitry has changed, and the on-circuit emulation (ONCE) special-purpose mode op- eration has changed slightly because of the new reset state pin levels ...
Page 96
X SUPPLEMENT F XTAL1 XTAL1 XTAL2 Disable Oscillator (Powerdown) Figure 10-1. Clock Circuitry (87C196LA, LB Only) 10.2 ENTERING AND EXITING ONCE MODE ONCE mode isolates the device from other components in the system to allow printed-circuit- board testing or ...
Page 97
If you choose to configure this pin as an input, always hold it low during reset and en- sure that your system meets the V SPECIAL OPERATING MODES specification to prevent inadvertent entry into ONCE mode. IH 10-3 ...
Page 98
...
Page 99
Programming the Nonvolatile Memory 11 ...
Page 100
...
Page 101
PROGRAMMING THE NONVOLATILE MEMORY The 87C196LA and LB microcontrollers contain 24 Kbytes (2000–7FFFH) of one-time-pro- grammable read-only memory (OTPROM). OTPROM is similar to EPROM, but it comes in a windowless package and cannot be erased. You have the option of ...
Page 102
X SUPPLEMENT Table 11-2. 87C196LA, LB OTPROM Address Map Address Range (Hex) 7FFF Program memory 2080 207F Reserved (each location must contain FFH) 205E 205D PTS vectors 2040 203F Upper interrupt vectors 2030 202F Security key 2020 201F Reserved ...
Page 103
V CC 0.1 µF EA# EA P0.7/PMODE.3 P0.6/PMODE.2 P0.5/PMODE.1 P0.4/PMODE.0 ANGND Figure 11-1. Slave Programming Circuit Table 11-3. Slave Programming Mode Address Map Description OTPROM OFD † DED † DEI PCCB Programming V CC Programming V ...
Page 104
X SUPPLEMENT 11.4 SERIAL PORT PROGRAMMING CIRCUIT AND ADDRESS MAP Figure 11-2 shows the circuit and Table 11-4 details the address map for serial port programming 0.01 µF RXD V CC 1.8k 1.8k 2N2907 ...
Page 105
Table 11-4. Serial Port Programming Mode Address Map Description Internal OTPROM External memory Do not address Test ROM and RISM PROGRAMMING THE NONVOLATILE MEMORY Address Range Normal Operation Serial Port Programming Mode 2000–7FFFH — — — A000–FFFFH 4000–9FFFH 2400–3FFFH 2000–23FFH ...
Page 106
...
Page 107
Signal Descriptions A ...
Page 108
...
Page 109
This appendix provides reference information for the pin functions of the 8XC196Lx microcon- trollers. A.1 FUNCTIONAL GROUPINGS OF SIGNALS Tables A-1, A-2, and A-3 list the signal assignments for the 8XC196Lx microcontrollers, grouped by function. A diagram of each microcontroller ...
Page 110
X SUPPLEMENT Table A-1. 87C196LA Signals Arranged by Functional Categories Addr & Data Input/Output (Cont’d) Name Pin AD0 22 P2.1 / RXD AD1 21 P2.2 AD2 20 P2.4 AD3 19 P2.6 AD4 18 P2.7 AD5 17 P3.0 AD6 16 ...
Page 111
AD14 / P4.6 / PBUS.14 8 AD13 / P4.5 / PBUS.13 9 AD12 / P4.4 / PBUS.12 10 AD11 / P4.3 / PBUS.11 11 AN87C196LA20 AD10 / P4.2 / PBUS.10 12 AD9 / P4.1 / PBUS.9 13 AD8 / P4.0 ...
Page 112
X SUPPLEMENT Table A-2. 87C196LB Signals Arranged by Functional Categories Addr & Data Input/Output (Cont’d) Name Pin AD0 22 P2.1 / RXD AD1 21 P2.2 AD2 20 P2.4 / RXJ1850 AD3 19 P2.6 / TXJ1850 AD4 18 P2.7 AD5 ...
Page 113
AD14 / P4.6 / PBUS.14 8 AD13 / P4.5 / PBUS.13 9 AD12 / P4.4 / PBUS.12 10 AD11 / P4.3 / PBUS.11 11 AN87C196LB20 AD10 / P4.2 / PBUS.10 12 AD9 / P4.1 / PBUS.9 13 AD8 / P4.0 ...
Page 114
X SUPPLEMENT Table A-3. 83C196LD Signals Arranged by Functional Categories Addr & Data Input/Output Name Pin Name AD0 22 P1.0/EPA0/T2CLK AD1 21 P1.1/EPA1 AD2 20 P1.2/EPA2/T2DIR AD3 19 P1.3/EPA3 AD4 18 P2.0/TXD AD5 17 P2.1/RXD AD6 16 P2.2 AD7 ...
Page 115
AD14 / P4.6 AD13 / P4.5 AD12 / P4.4 AD11 / P4.3 AD10 / P4.2 AD9 / P4.1 AD8 / P4.0 AD7 / P3.7 AD6 / P3.6 AD5 / P3.5 AD4 / P3.4 AD3 / P3.3 AD2 / P3.2 Figure ...
Page 116
X SUPPLEMENT Table A-5. 87C196LA, LB Default Signal Conditions Port Alternate Signals Functions P0.7:2 ACH7:2 P1.0 EPA0/T2CLK P1.1 EPA1 P1.2 EPA2/T2DIR P1.3 EPA3 P2.0 TXD P2.1 RXD P2.2 EXTINT P2.4 RXJ1850 (LB only) P2.6 ONCE/TXJ1850 (LB only) P2.7 CLKOUT ...
Page 117
Table A-6. 83C196LD Default Signal Conditions Port Alternate Signals Functions P0.7:2 — P1.0 EPA0/T2CLK P1.1 EPA1 P1.2 EPA2/T2DIR P1.3 EPA3 P2.0 TXD P2.1 RXD P2.2 EXTINT P2.4 — P2.6 ONCE P2.7 CLKOUT P3.7:0 AD7:0 P4.7:0 AD15:8 P5.0 ALE/ADV# P5.2 WR#/WRL# ...
Page 118
...
Page 119
Glossary ...
Page 120
...
Page 121
This glossary defines acronyms, abbreviations, and terms that have special meaning in this man- ual. (Chapter 1 discusses notational conventions and general terminology.) absolute error accumulator actual characteristic A/D converter ALU assert attenuation bit BIT bit arbitration break-before-make The maximum ...
Page 122
X SUPPLEMENT byte BYTE CCBs CCRs channel-to-channel matching error characteristic chip-select unit clear code code center code transition code width Glossary-2 Any 8-bit unit of data. An unsigned, 8-bit variable with values from 0 8 through 2 –1. Chip ...
Page 123
DC input leakage deassert demultiplexed bus differential nonlinearity doping double-word DOUBLE-WORD EPA ESD The detection of conflicting symbols or bits on the bus. See off-isolation. Leakage current from an analog input pin to ground or to the reference ...
Page 124
X SUPPLEMENT external address f far constants far data feedthrough FET full-scale error hold latency ideal characteristic input leakage input series resistance integer INTEGER Glossary-4 A 21-bit address is presented on the microcontroller’s pins. The address decoded by an ...
Page 125
J1850 ISR linearity errors LONG-INTEGER LSB LSW The 24-bit address that the microcontroller generates. See also external address. The module responsible for handling interrupts that are to be serviced ...
Page 126
X SUPPLEMENT maskable interrupts monotonic MSB MSW multiplexed bus n-channel FET n-type material near constants near data no missing codes Glossary-6 All interrupts except stack overflow, unimplemented opcode, and software trap. Maskable interrupts can be disabled (masked) by the ...
Page 127
FET p-type material PC phase-locked loop PIC PIH PLL The maximum deviation of code transitions of the terminal-based characteristic from the corre- sponding code transitions of the ideal characteristic. Interrupts that cannot be ...
Page 128
X SUPPLEMENT prioritized interrupt program memory protected instruction PSW PTS PTSCB PTS control block PTS cycle PTS interrupt PTS mode PTS routine PTS transfer Glossary-8 NMI, stack overflow, or any maskable interrupt. Two of the nonmaskable interrupts (unimplemented opcode ...
Page 129
PTS vector QUAD-WORD quantizing error RALU repeatability error reserved memory resolution sample capacitor sample delay sample delay uncertainty sample time A location in special-purpose memory that holds the starting address of a PTS control block. An unsigned, 64-bit variable with ...
Page 130
X SUPPLEMENT sample time uncertainty sample window sampled inputs SAR set SFR SHORT-INTEGER sign extension sink current source current SP special interrupt Glossary-10 The variation in the sample time. The period of time that begins when the sample capacitor ...
Page 131
UART A partition of memory used for storing the interrupt vectors, PTS vectors, chip configuration bytes, and several ...
Page 132
X SUPPLEMENT V rejection CC VPW wait state watchdog timer WDT word WORD zero extension zero-offset error Glossary-12 The property of an A/D converter that causes it to ignore (reject) changes that the actual CC characteristic ...
Page 133
Index ...
Page 134
...
Page 135
A Address map, 3-1 Address partitions map, 3-1 OTPROM, 11-1 program memory, 11-1 special-purpose memory, 11-1 ALE, idle, powerdown, reset status, A-8, A-9 B Block diagram 8XC196Lx, 2-2 C CLKOUT and internal timing, 2-2–2-4 idle, powerdown, reset status, A-8, A-9 ...
Page 136
P Period (t), 2-4 Port 0 idle, powerdown, reset status, A-8, A-9 overview, 5-1 Port 1 configuring, 5-3 idle, powerdown, reset status, A-8, A-9 overview, 5-1 Port 2 configuring, 5-3 idle, powerdown, reset status, A-8, A-9 overview, 5-1 P2.7 reset ...