74LVC2G34GV,125 NXP Semiconductors, 74LVC2G34GV,125 Datasheet - Page 6

• Manufacturer Part Number: 74LVC2G34GV,125
• Description: IC BUFFER DL NON-INVERTING 6TSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr

Specifications of 74LVC2G34GV,125

• Package / Case: SC-74-6
• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Current - Output High, Low: 32mA, 32mA
• Voltage - Supply: 1.65 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: LVC
• Number Of Channels Per Chip: 2
• Polarity: Non-Inverting
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.65 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 32 mA
• Input Bias Current (max): 40 uA
• Low Level Output Current: 32 mA
• Minimum Operating Temperature: - 40 C
• Propagation Delay Time: 2.5 ns (Typ) @ 2.7 V or 2.2 ns (Typ) @ 3.3 V or 1.9 ns (Typ) @ 5 V
• Number Of Lines (input / Output): 2 / 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74LVC2G34GV-G; 74LVC2G34GV-G; 935273784125

NXP Semiconductors
11. Dynamic characteristics
Table 8.
Voltages are referenced to GND (ground = 0 V); for load circuit see
[1]
[2]
[3]
12. Waveforms
74LVC2G34
Product data sheet
Symbol Parameter
t
C
pd
Fig 7.
PD
Typical values are measured at T
t
C
P
f
f
C
V
N = number of inputs switching;
∑(C
pd
i
o
D
CC
PD
= input frequency in MHz;
L
= output frequency in MHz;
is the same as t
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
× V
Measurement points are given in
Logic levels: V
propagation delay nA to nY; see
power dissipation
capacitance
The data input (nA) to output (nY) propagation delays
PD
Dynamic characteristics
CC
× V
2
× f
CC
o
2
) = sum of outputs.
× f
PLH
i
× N + ∑(C
OL
and t
and V
PHL
Conditions
V
OH
L
I
.
V
V
V
V
V
= GND to V
× V
amb
are typical output voltage levels that occur with the output load.
CC
CC
CC
CC
CC
CC
nA input
nY output
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 4.5 V to 5.5 V
= 25 °C and V
2
× f
Table
o
All information provided in this document is subject to legal disclaimers.
) where:
GND
Figure 7
CC
V
V
9.
OH
OL
V
; V
I
Rev. 5 — 2 September 2010
CC
CC
t
PLH
= 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
= 3.3 V
D
V
in μW).
M
V
M
[2]
[3]
Figure
Min
1.0
0.5
0.5
0.5
0.5
-
−40 °C to +85 °C
8.
V
M
V
Typ
M
3.8
2.4
2.5
2.2
1.9
20
t
mnb072
PHL
[1]
Max
8.6
4.4
5.0
4.1
3.2
-
74LVC2G34
−40 °C to +125 °C Unit
Min
1.0
0.5
0.5
0.5
0.5
-
© NXP B.V. 2010. All rights reserved.
Dual buffer gate
Max
10.8
5.5
6.3
5.1
4.0
-
6 of 17
pF
ns
ns
ns
ns
ns