XA-G49 NXP Semiconductors, XA-G49 Datasheet
XA-G49
Related parts for XA-G49
XA-G49 Summary of contents
Page 1
... XA-G49 XA 16-bit microcontroller family 64K FLASH/2K RAM, watchdog, 2 UARTs Preliminary data Supersedes data of 2000 Dec 01 IC28 Data Handbook hilips Semiconductors INTEGRATED CIRCUITS 2001 Jun 27 ...
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... Philips Semiconductors XA 16-bit microcontroller family 64K Flash/2K RAM, watchdog, 2 UARTs GENERAL DESCRIPTION The XA-G49 is a member of Philips’ 80C51 XA (eXtended Architecture) family of high performance 16-bit single-chip microcontrollers. The XA-G49 contains 64 kbytes of Flash program memory, and provides three general purpose timers/counters, a watchdog timer, dual UARTs, and four general purpose I/O ports with programmable output configurations ...
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... Plastic Leaded Chip Carrier –40 to +85 44-pin Plastic Leaded Chip Carrier 0 to +70 44-pin Plastic Low Profile Quad Flat Package XTAL1 XTAL2 RST EA/WAIT PSEN ALE 3 Preliminary data XA-G49 FREQ. DRAWING (MHz) NUMBER 30 SOT187-2 30 SOT187-2 30 SOT389-1 T2EX* T2 ...
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... LQFP Package Pin /WAIT SU01035 Preliminary data XA-G49 LQFP Function Pin Function P1.5/TxD1 23 P2.5/A17D13 P1.6/T2 24 P2.6/A18D14 P1.7/T2EX 25 P2.7/A19D15 RST 26 PSEN P3.0/RxD0 27 ALE P3.1/TxD0 29 EA/V /WAIT PP P3 ...
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... Timer 1 external input, or timer 1 overflow output. The value on this pin is latched as the external reset input is released and defines the default external data bus width (BUSW 8-bit bus and 1 = 16-bit bus. WRL (P3.6): External data memory low byte write strobe. RD (P3.7): External data memory read strobe. 5 Preliminary data XA-G49 ...
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... T2EX T2 TxD1 RxD1 397 396 395 394 432 P2.7 P2.6 P2.5 P2.4 39F 39E 39D 39C 433 Preliminary data XA-G49 RESET VALUE LSB — — — — BUSD BC2 BC1 BC0 Note 1 DR1 DR0 DRA1 DRA0 FF CR1 CR0 CRA1 CRA0 ...
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... ESWEN R6SEG R5SEG R4SEG 47A — SWE7 SWE6 SWE5 7 Preliminary data XA-G49 RESET RESET VALUE VALUE LSB Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 223 222 221 220 — — PD ...
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... The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes. 7. The XA-G49 implements an 8-bit SFR bus, as stated in Chapter 8 of the XA User Guide . All SFR accesses must be 8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte. ...
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... DATA MEMORY (DIRECTLY AND INDIRECTLY ADDRESSABLE, ON CHIP) 2001 Jun BYTES TOTAL CODE MEMORY 2k BYTE BOOT ROM 64k BYTES ON-CHIP CODE MEMORY Figure 1. XA-G49 Program Memory Map FFFFFh FFFFFh 0800h 07FFh 0400H 03FFh DIRECTLY ADDRESSED DATA (1k PER SEGMENT) 0040h 003Fh ...
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... CAPABILITIES OF THE PHILIPS XA-G49 FLASH-BASED MICROCONTROLLERS Flash organization The XA-G49 contains 64 kbytes of Flash program memory. This memory is organized as 5 separate blocks. The first two blocks are 8 kbytes in size, filling the program memory space from address 0 through 3FFF hex. The final three blocks are 16 kbytes in size and occupy addresses from 4000 through FFFF hex ...
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... The “Boot Vector” allows forcing the execution of a user supplied Flash loader upon reset, under two specific sets of conditions. At the falling edge of reset, the XA-G49 examines the contents of the Status Byte. If the Status Byte is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’ ...
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... ISP facility. The maximum number of data bytes in a record is limited to 16 (decimal). ISP commands are summarized in Table record is received by the XA-G49, the information in the record is stored internally and a checksum calculation is performed. The operation indicated by the record type is not performed until the entire record has been received. Should an error occur in the checksum, the XA-G49 will send an “ ...
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... Any user supplied loader should take the watchdog timer into account. Typically, the watchdog timer would be disabled upon entry to the loader if it might be running, in order to prevent a watchdog reset from occurring during programming. 13 Preliminary data XA-G49 ...
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... NOTE: Only two bits of these Special Cells may be programmed at one time. Example: :020000830601FC78 2001 Jun 27 COMMAND/DATA FUNCTION erase block 1 erase boot vector and status byte (inhibit writing to FLASH) (inhibit FLASH verify) (disable external memory) program security bit 2 program boot vector to FC00h 14 Preliminary data XA-G49 ...
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... Example: :02000085000178 2001 Jun 27 COMMAND/DATA FUNCTION display 4000–4FFF read signature byte – device Preliminary data XA-G49 (EAH) (XA–G49 = 54H)) ...
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... PGM_MTP. The programming functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at FFF0H. Results are returned in the registers. The API calls are shown in Table 2. PARAMETER 01h – security bit # 2 (inhibit FLASH verify) 02h – security bit # 3 (disable external memory) 16 Preliminary data XA-G49 ...
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... BPSW[7:0] 0001h: program BPSW[15:8] 0002h: program BPC[7:0] 0003h: program BPC[15:8] 0004h: program status byte 000Ah: program security bit #1 000Ch: program security bit #2 000Eh: program security bit #3 17 Preliminary data XA-G49 ...
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... The security feature protects against software piracy and prevents the contents of the Flash from being read. The Security Lock bits are located in Flash. The XA-G49 has 3 programmable security lock bits that will provide different levels of protection for the on-chip code and data (see Table 3) ...
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... Philips Semiconductors XA 16-bit microcontroller family 64K Flash/2K RAM, watchdog, 2 UARTs XA-G49 TIMER/COUNTERS The XA has two standard 16-bit enhanced Timer/Counters: Timer 0 and Timer 1. Additionally, it has a third 16-bit Up/Down timer/counter, T2. A central timing generator in the XA core provides the time-base for all XA Timers and Counters. The timer/event counters can perform the following functions: – ...
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... When Timer Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator fact, in any application not requiring an interrupt. TR1 TF0 TR0 IE1 IT1 20 Preliminary data XA-G49 LSB IE0 IT0 SU00604C ...
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... TL2 and TH2, respectively. A logic ‘0’ at pin T2EX causes Timer 2 to count down. When counting down, the timer value is compared to the 16-bit value contained in T2CAPH and T2CAPL. When the value is equal, the 21 Preliminary data XA-G49 LSB C/T2 CP/RL2 SU01385 ...
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... T2EX pin X X — — — — T1OE — RCLK1 TCLK1 — — Figure 10. Timer 2 Mode Control (T2MOD) 22 Preliminary data XA-G49 TCLK MODE Timer off (stopped) 16-bit capture Baud rate generator LSB — T0OE SU00612B LSB T2OE DCEN SU00610B ...
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... Control TR2 Reload T2CAPL T2CAPH Control (DOWN COUNTING RELOAD VALUE) FFH FFH OVERFLOW TL2 TH2 T2CAPL T2CAPH (UP COUNTING RELOAD VALUE) 23 Preliminary data XA-G49 TF2 Timer 2 Interrupt EXF2 SU00704 TF2 Timer 2 Interrupt EXF2 SU00705 TOGGLE EXF2 TF2 INTERRUPT COUNT DIRECTION ...
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... When coming out of a hardware reset, the software should load the autoload register and then feed the watchdog (cause an autoload). If the watchdog is running and happens to underflow at the time the external RESET is applied, the watchdog time-out flag will be cleared. 24 Preliminary data XA-G49 4096 t and the OSC PRE0 DIVISOR ...
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... Timeout flag WDCON.0 — UARTs The XA-G49 includes 2 UART ports that are compatible with the enhanced UART used on the 8xC51FB. Baud rate selection is somewhat different due to the clocking scheme used for the XA timers. Some other enhancements have been made to UART operation. ...
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... If there is any possibility that a higher priority interrupt might become active between the write to SnBUF and the clearing of the TI_n flag, the interrupt system may have to be temporarily disabled during that sequence by clearing, then setting the EA bit in the IEL register. 26 Preliminary data XA-G49 ...
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... T2CON 0x418 T2MOD 0x419 Prescaler Select for Timer Clock (TCLK) SCR 0x440 — — — — FEn (See also Figure 17 regarding Framing Error flag) 27 Preliminary data XA-G49 bit5 bit4 RCLK0 TCLK0 bit5 bit4 RCLK1 TCLK1 bit3 bit2 PT1 PT0 LSB BRn ...
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... Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature. 28 Preliminary data XA-G49 1100 0000 1111 1101 = 1100 00X0 1100 0000 ...
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... FEn BRn Figure 17. UART Framing Error Detection SM0_n SM1_n SM2_n REN_n COMPARATOR 29 Preliminary data XA-G49 LSB TB8 RB8 TI RI SU00597C ONLY IN STOP MODE 2, 3 BIT if 0, sets FE SnSTAT OEn STINTn SU00598 D7 D8 SnCON TB8_n ...
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... POWER REDUCTION MODES The XA-G49 supports Idle and Power Down modes of power reduction. The idle mode leaves some peripherals running to allow them to wake up the processor when an interrupt is generated. The power down mode stops the oscillator in order to minimize power. ...
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... IEL or IEH registers). Only three bits of the IPA register values are used on the XA-G49. Each event interrupt can be set to occur at one of 8 priority levels via bits in the Interrupt Priority (IP) registers, IPA0 through IPA5 ...
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... DDmin 3.2mA DDmin 5.25 V must be externally limited as follows V Preliminary data XA-G49 RATING UNIT –55 to +125 C –65 to +150 +13.0 V –0 +0 1.5 W LIMITS UNIT UNIT MIN TYP MAX 110 mA ...
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... V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1. 2001 Jun 5.25 V, – +85 C for industrial. DD PARAMETER PARAMETER ( ( ( ( ( (V12 * t (V13 * t (V11 * t ( (V11 * t (V10 * t 33 Preliminary data XA-G49 VARIABLE CLOCK UNIT UNIT MIN MAX 0 30 MHz 1 0 ...
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... This would be A3–A0 for an 8-bit bus, and A3–A1 for a 16-bit bus. Also, a 16-bit data read operation conducted on a 8-bit wide bus similarly does not include two separate RD strobes. So, a rising edge on the low order address line (A0) must be used to trigger a WAIT in the second half of such a cycle. 2001 Jun 27 34 Preliminary data XA-G49 ...
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... Please note that the XA-G49 requires that extended data bus hold time (WM0 = used with external bus write cycles. 7. Applies only to an external clock source, not when a crystal or ceramic resonator is connected to the XTAL1 and XTAL2 pins. ...
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... UNMULTIPLEXED ADDRESS Figure 23. External Data Memory Read Cycle (Non-ALE Cycle) 2001 Jun LLRL RLRH t RHDZ t RLDV t RHDX * DATA AVDVA A0 or A1–A3, A12–A19 D0–D7 A0–A3, A12–A19 36 Preliminary data XA-G49 DXUA SU00947 * DATA IN t AVDVB A0–A3, A12–A19 SU00708A ...
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... RD, OR PSEN) t WTH 2001 Jun WLWH LLWL t QVWX * DATA OUT A1–A3, A12–A19 Figure 24. External Data Memory Write Cycle (The dashed line shows the strobe without WAIT.) t WTL Figure 25. WAIT Signal Timing 37 Preliminary data XA-G49 t WHQX UAWH SU00584C SU00709A ...
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... DD Figure 27. AC Testing Input/Output +0.1V TIMING REFERENCE POINTS –0.1V /V level occurs Figure 28. Float Waveform (NC) CLOCK SIGNAL SU00591B Figure 30 Preliminary data XA-G49 SU00842 SU00703A V –0. +0. 20mA SU00011 RST EA XTAL2 ...
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... Tests in Active and Idle Modes 5ns CLCH CHCL RST EA (NC) XTAL2 XTAL1 V SS SU00585A Test Condition, Power Down Mode DD All other pins are disconnected 5 Preliminary data XA-G49 MAX. I (ACTIVE) DD MAX. I (IDLE SU00844 SU00608A ...
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... Philips Semiconductors XA 16-bit microcontroller family 64K Flash/2K RAM, watchdog, 2 UARTs PLCC44: plastic leaded chip carrier; 44 leads 2001 Jun 27 40 Preliminary data XA-G49 SOT187-2 ...
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... Philips Semiconductors XA 16-bit microcontroller family 64K Flash/2K RAM, watchdog, 2 UARTs LQFP44: plastic low profile quad flat package; 44 leads; body 1.4 mm 2001 Jun 27 41 Preliminary data XA-G49 SOT389-1 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors 2001 Jun 27 Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Document order number: 42 Preliminary data XA-G49 Date of release: 06-01 9397 750 08524 ...