XA-SCC NXP Semiconductors, XA-SCC Datasheet
XA-SCC
Related parts for XA-SCC
XA-SCC Summary of contents
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... XA-SCC CMOS 16-bit communications microcontroller Preliminary specification IC25 Data Handbook INTEGRATED CIRCUITS 1999 Feb 23 ...
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... Philips Semiconductors CMOS 16-bit communications microcontroller GENERAL DESCRIPTION The XA-SCC device is a member of Philips’ XA (eXtended Architecture) family of high performance 16-bit single-chip microcontrollers. The XA-SCC includes a complete onboard DRAM controller capable of supporting up to 32MegaBytes of DRAM. The XA-SCC device combines many powerful communications oriented peripherals on one chip. 4 Full Function SCC’ ...
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... P0.6_SCPTx 99 P0.7_SCPRx 100 NOTE: Address lines output during various DRAM CAS cycles are shown in parentheses. See DRAM controller for details. 1999 Feb 23 XA-SCC PLASTIC LOW PROFILE QUAD FLAT PACKAGE (LQFP) Top View 3 Preliminary specification XA-SCC CS0 48 CS1_RAS1 47 CS2_RAS2 46 CS3_RAS3 45 ClkOut ...
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... RxD2 1.0 TxD2 1.1 RTClk2 1.2 TRClk2 1.3 CD2 1.4 CTS2 1.5 RTS2 1.6 1.7 SCC0 PORT0 TxD0 RxD0 0.0 0.1 0.2 CD0 0.3 0.4 0.5 0.6 0.7 4 Preliminary specification XA-SCC XTAL1 XTAL2 CS3, RAS3 CS2, RAS2 CS1, RAS1 CS0 A19 – DRAM A22 – A0) D15 – D0 ClkOut CASH, BHE CASL, BLE OE WE Wait, Size16 ResetIn SU01121 ...
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... Feb 23 RESET INTERRUPT 256 BYTES CONTROL & CONTROLLER RAM STATUS AUTOBAUD x4 IDL INTERFACE DMA SCCs x4 x8 v.54 2047 x2 Figure 1. XA-SCC Block Diagram 5 Preliminary specification XA-SCC TIMERS 0,1 WATCHDOG TIMER SCP SCP PORT INTERFACE PORTS and PIN GPIO FUNCTION MUX IDL and NMSI PORTS ...
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... CS2 , RAS 2: Active low chip selects CS1 through CS5 come out of reset disabled. They can be programmed to function as normal chip selects RAS strobes to DRAM. CS2 through CS5 are not used with the “SWAP” operation (see Memory Controller chapter in the XA-SCC User Manual.) They are mappable to any region of the 16MB address space. ...
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... GPIO pins, during power up reset, this pin can output a strongly driven low pulse. The duration of this low pulse ranges from 0ns to 258 system clocks, starting at the time that V ResetIn pin does not affect this pulse. When used as GPIO, this pin can also be driven low by software without resetting the XA-SCC. P3.3 63 I/O P3 ...
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... BIT FUNCTIONS AND ADDRESSES MSB WARNING—Never write to the BCR register in the XA-SCC part—it is initialized to 07h, the only legal value. This is not the same as for other XA derivatives. WARNING—Immediately after reset, always write BTRH = 51h, followed by writing BTRL = 40h in that order Follow these two writes with five NOPS This is not the BTRL = 40h in that order ...
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... PT1 21F 21E 21D 21C 21B ESWEN R6SEG R5SEG R4SEG R3SEG 9 Preliminary specification XA-SCC RESET LSB VALUE 39A 399 398 FFh Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 222 221 220 – PD ...
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... SFRs marked with a pound sign (#) are additional SFR registers specific to the XA-SCC. 1. The XA-SCC implements an 8-bit SFR bus, as stated in Chapter 8 of the IC25 Data Handbook XA User Guide. All SFR accesses must be 8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte ...
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... Transmit Data Buffer R/W 8 852h Master Interrupt control R/W 8 854h Misc. Tx/Rx control register R/W 8 856h Clock Mode Control R/W 8 858h Lower Byte of Baud rate time constant 11 Preliminary specification XA-SCC Reset Description Value 00h xx xx 00h 00h 00h 00h 00h xx 00h 00h xx f8h 00h 00h — ...
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... SDLC byte count low register RO 8 8AEh SDLC byte count high & FIFO status RO 8 8B0h Receive Buffer 8B2h RO 8 8B4h Loop/clock status 8B6–8BEh 12 Preliminary specification XA-SCC Reset Description Value 00h xx f8h 00h 00h — — — — — — — — ...
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... R/W 8 110h Control Register R/W 8 111h Control & Status Register R/W 8 112h Points to 64K data segment R/W 8 114h Wrap Reload Value for A15 –A8, A7–A0 reloaded to zero by hardware 13 Preliminary specification XA-SCC Reset Description Value 00h xx xx 00h 00h 00h 00h 00h xx 00h 00h xx f8h ...
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... Byte2 = older 14F = Byte3 = younger R/W 8 150h Control Register R/W 8 151h Control & Status Register R/W 8 152h Points to 64K data segment 14 Preliminary specification XA-SCC Reset Description Value 0000h 0000h 0000h 00h 00h 00h 00h 00h 00h 00h 00h 0000h 0000h 0000h 00h ...
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... V.54 2047 Unit B Configuration R/W 8 24Ah V.54 2047 Unit B Threshold Cntr Lo R/W 8 24Bh V.54 2047 Unit B Threshold Cntr Hi R/W 8 24Ch V.54 2047 Unit B Error Counter 15 Preliminary specification XA-SCC Reset Description Value 00h 0000h 0000h 0000h 0000h 0000h 00h 00h 00h 00h 0000h 0000h 0000h 0000h ...
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... IDL Mode Control Register R/W 16 2C2h IDL Mask Register Miscellaneous Registers R/W 16 2D0h Control bits for Hi-Priority Soft Ints, and Pin Mux R/W 8 2D2h External Interrupt 2 Control 16 Preliminary specification XA-SCC Reset Description Value 8xh xx 00h 00h .. 00h .. — 00h.. — 0xh xxh xxh 0xh ...
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... Because ResetOut does not reflect ResetIn, the ResetOut pin can be tied directly back into the ResetIn pin without other PC board logic. This configuration will make all resets (internal or external) appear to the XA as external resets. See the XA-SCC User Manual for a full discussion of the reset functions. ResetIn The ResetIn function is the standard XA-G3 ResetIn function ...
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... Chip select output pins function as either CS or RAS depending on whether the memory bank has been programmed as generic or DRAM. The XA-SCC has a highly programmable memory bus interface with a complete onboard DRAM controller. Most DRAMs (up to 8MBytes per RAS pin), SRAMs, Flash, ROMs, and peripheral chips can be connected to this interface with zero glue chips ...
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... DRAM): bank on/off, address range, external device access time, WARNING: On the external bus, ALL XA-SCC reads are 16 bit Reads. If the CPU instruction only specifies 8 bits, then the CPU uses the appropriate byte, and discards the extra byte. Thus “8 Bit Reads” appear to be identical on the bus bit bus, this will appear as two consecutive 8 bit reads even though the CPU instruction specified a byte read Some 8 bit I/O devices (especially FIFOs) cannot operate correctly with 2 bytes being Read for a 1 Byte Read ...
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... During DRAM cycles only, the appropriate CAS Address will be multiplexed onto pins A17–A7 after the assertion or RAS and prior to the assertion of BHE (CASH) and BLE (CASL). See AC timing diagrams and the XA–SCC User Manual for complete details. 1999 Feb 23 A17–A9 D15–D0 A17–A8 Figure 5. Typical System Bus Configuration 20 Preliminary specification XA-SCC CS OE 128K x 8 ROM A16–A0 D7–D0 RAS CASL CASH ...
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... Type This SFR is used to relocate the MMRs. It contains address bits a23–a16 of the base address for the 4 KByte Memory Mapped Register space. See XA-SCC User Manual for using this SFR to relocate the MMRs. Contains address bits a15–a12 of the base address for the 4 KByte Memory Mapped Register space ...
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... Byte Count can be calculated by Character Match software from the DMA address pointer. 1999 Feb 23 summarized in the following table. For full details on implementation and use, see the XA-SCC User Manual. Maskable Interrupt At end of received packet When Byte Counter reaches zero and is reloaded by DMA hardware from the byte count register ...
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... IDL. If there are pins not being used by any of the SCCs, software can assign alternate functions to those pins; see the pin steering logic in the “Pins” appendix of the XA-SCC User Manual. For complete documentation on the IDL interface, see the IDL chapter in the XA-SCC User Manual. ...
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... The XA-SCC has a standard XA CPU Interrupt Controller, implemented with 15 Maskable Event Interrupts. Event Interrupts are defined as maskable interrupts usually generated by hardware events. However, in the XA-SCC the 15 Event Interrupts are generated by software writing directly to the interrupt flag bit. These 4 interrupts are referred to as High Priority Software Interrupts. ...
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... AUTOBAUD 3–0 v.54_2047 1–0 SCP INTERFACE TIMER 0 TIMER 1 HIGH PRIORITY SOFTWARE INTS HSWR 3–0 1999 Feb 23 DMAH DMAL INTERRUPT ENABLE/ DISABLE BITS OR 4 Figure 8. XA-SCC Interrupt Structure Overview 25 Preliminary specification XA-SCC XA CORE INTERRUPT CONTROLLER INTERRUPT TO XA CPU MASTER ENABLE “EA” SU01129 ...
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... WR1[0] RR3[3] RR0[3] RR0[1] VECTOR ADDRESS 0000–0003 0004–0007 0008–000B 000C–000F 0010–0013 0014–0017 0040–007F 26 Preliminary specification XA-SCC Master Enable Bit Hex Offset MMR Hex Offset SCC0/1 Master Interrupt Enable WR9[3] ARBITRATION RANKING 0 (High ...
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... VECTOR ADDRESS ENABLE BIT 0100–0103 SWE1 0104–0107 SWE2 0108–010B SWE3 010C–010F SWE4 0110–0113 SWE5 0114–0117 SWE6 0118–011B SWE7 27 Preliminary specification XA-SCC Priority Register Bit Field (SFR) Arb. Rank PHSWR3 17 PHSWR2 16 PHSWR1 15 PHSWR0 14 PSCP 13 PAutoB 12 PSC23 11 ...
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... 5. 3.6V DD must be externally limited as follows: OL 15mA (*NOTE: This specification for V 26mA 71mA 28 Preliminary specification XA-SCC RATING UNIT –55 to +125 C –65 to +150 C –0 +0. 1.5 W LIMITS UNIT UNIT MIN TYP MAX 75 120 ...
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... WAIT setup (stable high or low) to CLKOUT rising edge WAIT hold (stable high or low) after CLKOUT rising edge WH NOTE: 1. See notes after the 3.3V AC timing table. 1999 Feb 23 1 10%) PARAMETER Preliminary specification XA-SCC LIMITS MIN MAX UNIT 0 30 MHz 33.33 – 0.5 – 0.4 – – ...
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... On all EDO DRAM reads and fetches, hold data valid on the bus until a new CAS is asserted, or until OE goes high (inactive avoid tri-state fights during read cycles and fetch cycles, do not drive data bus until OE goes active 1999 Feb 23 10%) PARAMETER Preliminary specification XA-SCC LIMITS UNIT MIN MAX 0 30 MHz 33.33 – 0.5 – ...
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... ClkOut) = 80pF. 6. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-SCC User Manual for details. 7. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from bytes long bit bus, A3– ...
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... Figure 10. Generic Memory (SRAM, ROM, Flash, etc.) Burst Code Fetch on 16 Bit Bus 1999 Feb CHSL AHDR t CHSH t (NOTE 2) DIH t DIS t t CHAV CHAV ADDRESS + DIH t DIH t DIS DIS NOTE 2 NOTE 2 32 Preliminary specification XA-SCC t CHAH (DOES NOT INCLUDE A0) SU01130 ADDRESS + 4 t CHSH t OHDE t (NOTE 2) DIH t DIS DRIVEN BY XA SU01131 ...
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... RAS ADDRESS t CHAV t CHSL t AVSL RAS (CS) CAS (BHE/BLE 1999 Feb 23 t CHSH t CHSL t SHAH NOTE 1 t SHDH CAS ADDRESS t CHAV t CHSH t CHSL t AVSL t DIS VALID DATA Figure 12. DRAM Single Read Cycle 33 Preliminary specification XA-SCC SU01132 t CHSH t OHDE t DIH NOTE 2 SU01133 ...
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... CPWH t NOTE 4 DIS WORD (from CAS ADDR CHSL CHAV CAS ADDRESS t CHAH t CHAH t CHSH t AVSL t NOTE 2 DIS INSTRUCTION 34 Preliminary specification XA-SCC CHAH t CHSH t CPWL t OHDE t NOTE 4 DIS WORD (from CAS ADDR + 2) SU01134 t CHAV CAS ADDRESS + 2 t CHAH t CHSH t CPWH NOTE 2 t ...
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... Figure 16. Generic (SRAM, Flash, I/O Device, etc.) Read (16 Bit or 8 Bit Bit Bus 1999 Feb 23 t CHSL CAS ADDRESS t NOTE 1 AVSL VALID DATA ODD BYTE ADDRESS t CHAV t NOTE 2 DIH t t DIS DIS NOTE 2 35 Preliminary specification XA-SCC t CHAH t CHSH t CHSH SU01136 t AHDR t CHSH t OHDE DRIVEN BY XA SU01137 ...
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... DIH DIH DIH t t DIS DIS Note 2 Note 2 Note 2 MS BYTE LS BYTE t SHAH t t SHDH Figure 18. Generic 16 Bit Write on 8 Bit Bus 36 Preliminary specification XA-SCC t CHAV ADDRESS + 3 t CHSH t DIH t DIS Note 2 MS BYTE SU01138 t CHSH t SHAH t AVSL DVSL SU01139 ...
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... AVSL t DIS LS BYTE CAS ADDR CAS ADDR (ODD) (EVEN) t CHSH t CPWH t (NOTE 2) DIH LS BYTE MS BYTE 37 Preliminary specification XA-SCC t CHAV CAS ADDRESS ODD t CHAH t CHSH t CHSH t CPWH NOTE 2 t (NOTE 2) t DIH DIS MS BYTE SU01140 CAS ADDR ...
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... CPWH t NOTE 4 DIS LS BYTE MS BYTE t t CHSL CHAV CAS ADDRESS (EVEN) t CHAH t CHAH t CHSH t AVSL t CPWH t DVSL LS BYTE 38 Preliminary specification XA-SCC CAS ADDR (ODD) t CHSH t CHSH t OHDE NOTE 4 LS BYTE MS BYTE SU01142 t CHAV CAS ADDRESS (ODD) t CHAH t CHSH t DVSL ...
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... WARNING: ClkOut is specified into 40 pF max, do not overload. 1999 Feb 23 t CHSH Figure 23. REFRESH t RP Figure 24. RAS Precharge Time 0 – 0 CHCL CLCX t C Figure 25. External Clock Input Drive t CODH Figure 26. ClkOut Duty Cycle 39 Preliminary specification XA-SCC SU01144 SU01145 t CHCX t CLCH SU01146 SU01147 ...
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... Philips Semiconductors CMOS 16-bit communications microcontroller ClkOut WAIT t – Setup time of WAIT to riasing edge of ClkOut – Hold time of WAIT after ClkOut High. WH 1999 Feb Figure 27. External WAIT Pin Timing 40 Preliminary specification XA-SCC SU01148 ...
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... Philips Semiconductors CMOS 16-bit communications microcontroller LQFP100: plastic low profile quad flat package; 100 leads; body 1.4 mm 1999 Feb 23 41 Preliminary specification XA-SCC SOT407-1 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1999 Feb 23 [1] Copyright Philips Electronics North America Corporation 1999 Document order number: 42 Preliminary specification XA-SCC All rights reserved. Printed in U.S.A. Date of release: 02-99 9397 750 05291 ...