XA-SCC NXP Semiconductors, XA-SCC Datasheet - Page 21

• Manufacturer Part Number: XA-SCC
• Description: Cmos 16-bit Communications Microcontroller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 3. Memory Interface Control Registers
Eight Channel DMA Controller
The XA-SCC has eight DMA channels; one Rx DMA channel
dedicated to each SCC Receive (Rx) channel, and one Tx DMA
channel dedicated to each SCC Transmit (Tx) channel. All DMA
channels are optimized to support memory efficient circular data
buffers in external memory. All DMA channels can also support
traditional linear data buffers.
Table 4. Tx DMA Modes Summary
1999 Feb 23
BiCFG
MRBH
MRBL
MICFG
MBCL
BiAM
BiTMG
RFSH
Non-SDLC/HDLC
Tx Chaining
SDLC/HDLC
Tx Chaining
Stop on TC
Periodic Interrupt
CMOS 16-bit communications microcontroller
Mode
“MMR Base Address” Low
“MMR Base Address”
High
MIF Configuration
Memory Bank
Configuration Lock
Bank i Configuration
Bank i Base
Address/DRAM Address
Multiplexer Control
Refresh Timing
Bank i Timing
Register Name
Header in memory
Header in memory
Processor loads Byte Count
Register (for each fragment)
Processor loads Byte Count
Register (only once)
Byte Count Source
SFR
8 bits
SFR
8 bits
MMR
8 bits
MMR
8 bits
MMR
8 bits
MMR
8 bits
MMR
8 bits
MMR
8 bits
Type
Reg
This SFR is used to relocate the MMRs. It contains address bits a23–a16 of the
base address for the 4 KByte Memory Mapped Register space. See XA-SCC User
Manual for using this SFR to relocate the MMRs.
Contains address bits a15–a12 of the base address for the 4 KByte Memory
Mapped Register space.
Contains the CLKOUT Enable bit.
Contains the bits for locking and unlocking the BiCFG Registers.
Contains the size, type, bus width, and enable bits for Memory Bank i.
Contains the base address bits and DRAM address multiplex control bits for
Memory Bank i.
Contains the timing control bits for Memory Bank i.
Contains the refresh time constant and DRAM Refresh Timer enable bit.
On stop
End of packet (not
end of fragment)
Byte count completed
(Tx DMA stops)
Each time byte count
completed (Tx DMA
continues)
Maskable Interrupt
21
Transmit DMA Channel Modes
The four Tx channels have four DMA modes specifically designed
for various applications of the attached SCCs. These modes are
summarized in the following table. Full details for all DMA functions
can be found in the DMA chapter of the XA-SCC User Manual.
DMA channel picks up header from memory at
end of transmission. If byte count in header is
greater than zero, then DMA transmits the
number of bytes specified in the byte count. If
byte count equals 0, then a maskable interrupt is
generated. This process repeats until byte count
in data header is zero. See XA-SCC User
manual for details.
Same as above, except DMA header
distinguishes between fragment of packet and
full pack. See XA-SCC User manual for details.
Processor loads byte count into DMA. DMA
sends that number of bytes, generates maskable
interrupt, and stops.
DMA runs until commanded to stop by
processor. Everytime byte counter rolls over, a
new maskable interrupt is generated.
Description
Description
Preliminary specification
XA-SCC