ATA5760 ATMEL Corporation, ATA5760 Datasheet - Page 21

• Manufacturer Part Number: ATA5760
• Description: Ata5760 Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

10. Digital Noise Suppression
10.1
Figure 10-1. Output of Digital Noise at the End of the Data Stream
4896C–RKE–04/06
Automatic Noise Suppression
Data_out (DATA)
DATA_CLK
Bit-check
mode
Bit check ok
Figure 9-6.
After a data transmission, digital noise appears on the data output (see
Preventing that digital noise keeps the connected microcontroller busy. It can be suppressed in
two different ways.
If the bit Noise_Disable
receiver changes to bit-check mode at the end of a valid data stream. The digital noise is sup-
pressed and the level at pin DATA is High in that case. The receiver changes back to receiving
mode, if the bit check was successful.
This way to suppress the noise is recommended if the data stream is Manchester or Bi-phase
coded and is active after power on.
Figure 10-3 on page 22
Note that if the last period of the data stream is a high period (rising edge to falling edge), a
pulse occurs on pin DATA. The length of the pulse depends on the selected baud-rate range.
Preburst
Receiving mode,
data clock control
logic active
Timing Characteristic of the Data Clock (Falling Edge of the Pin DATA)
Data
Data_Out
Serial bi-directional
data line
Data_In
DATA_CLK
(Table 11-9 on page
illustrates the behavior of the data output at the end of a data stream.
Digital Noise
Receiving mode,
bit check aktive
Digital Noise
t
Delay1
t
Delay
25) in the OPMODE register is set to 1 (default), the
Bit check ok
t
Delay2
t
P_Data_Clk
Preburst
Receiving mode,
data clock control
logic active
V
V
V
IH
II
X
= 0.35
= 0.65
ATA5760/ATA5761
Data
V
V
S
S
Receiving mode,
bit check aktive
Figure 10-1 on page
Digital Noise
21).
21