ATA5760 ATMEL Corporation, ATA5760 Datasheet - Page 9

• Manufacturer Part Number: ATA5760
• Description: Ata5760 Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

6. Polling Circuit and Control Logic
7. Basic Clock Cycle of the Digital Circuitry
4896C–RKE–04/06
The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor-
responding transmitter. This is achieved via the polling circuit. This circuit enables the signal
path periodically for a short time. During this time the bit-check logic verifies the presence of a
valid transmitter signal. Only if a valid signal is detected, the receiver remains active and trans-
fers the data to the connected microcontroller. If there is no valid signal present, the receiver is
in sleep mode most of the time resulting in low current consumption. This condition is called poll-
ing mode. A connected microcontroller is disabled during that time.
All relevant parameters of the polling logic can be configured by the connected microcontroller.
This flexibility enables the user to meet the specifications in terms of current consumption, sys-
tem response time, data rate etc.
Regarding the number of connection wires to the microcontroller, the receiver is very flexible. It
can be either operated by a single bi-directional line to save ports to the connected microcontrol-
ler or it can be operated by up to five uni-directional ports.
The complete timing of the digital circuitry and the analog filtering is derived from one clock. This
clock cycle T
cuit. According to section
is defined by the RF input signal (f
oscillator (f
and T
T
Most applications are dominated by two transmission frequencies: f
used in USA, f
parameters on this electrical characteristics display three conditions for each parameter.
The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range)
which is defined in the OPMODE register. This clock cycle T
mulas for further reference:
BR_Range =
Clk
• Timing of the polling circuit including bit check
• Timing of the analog and digital signal processing
• Timing of the register programming
• Frequency of the reset marker
• IF filter center frequency (f
• Application USA (f
• Application Europe
• Other applications The electrical characteristic is given as a function of T
(f
(f
controls the following application-relevant parameters:
XTO
XTO
Clk
= 6.77617 MHz, T
= 6.77587 MHz, T
= 1.961 µs for f
LO
Clk
). The basic clock cycle is T
Transmit
is derived from the crystal oscillator (XTO) in combination with a divide by 14 cir-
XTO
= 868.3 MHz in Europe. In order to ease the usage of all T
RF
= 7.14063 MHz, T
“RF Front End” on page
= 915 MHz.
Clk
Clk
= 2.066 µs) for B
= 2.066 µs) for B
IF0
BR_Range0:
BR_Range1:
BR_Range2:
BR_Range3:
)
RFin
) which also defines the operating frequency of the local
Clk
Clk
= 14/f
IF
IF
= 1.961 µs)
= 600 kHz
= 300 kHz
XTO
4, the frequency of the crystal oscillator (f
giving T
T
T
T
T
XClk
XClk
XClk
XClk
ATA5760/ATA5761
= 8
= 4
= 2
= 1
XClk
Clk
= 2.066 µs for f
is defined by the following for-
T
T
T
T
Clk
Clk
Clk
Clk
Transmit
= 915 MHz is mainly
Clk
.
RF
Clk
= 868.3 MHz
-dependent
XTO
9
)