MC56F836 Freescale Semiconductor, Inc, MC56F836 Datasheet - Page 13

• Manufacturer Part Number: MC56F836
• Description: 56f8300 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Preliminary
1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced
pdb_m[15:0]
cdbw[15:0]
pab[20:0]
cdbr_m[31:0]
cdbw[31:0]
xab1[23:0]
xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads.
xab2[23:0]
IPBus [15:0]
to 0.
Name
Program data bus for instruction word fetches or read operations.
Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus
are used for writes to program memory.)
Program memory address bus. Data is returned on pdb_m bus.
Primary core data bus for memory reads. Addressed via xab1 bus.
Primary core data bus for memory writes. Addressed via xab1 bus.
Primary data address bus. Capable of addressing bytes
on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.
Secondary data address bus used for the second of two simultaneous accesses. Capable of
addressing only words. Data is returned on xdb2_m.
Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate
as the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.
Primary Data Memory Interface Bus
Secondary Data Memory Interface
Table 1-2 Bus Signal Names
56F8365 Technical Data, Rev. 7
Program Memory Interface
Peripheral Interface Bus
Function
1
, words, and long data types. Data is written
Architecture Block Diagram
13