MC56F836 Freescale Semiconductor, Inc, MC56F836 Datasheet - Page 80

no-image

MC56F836

Manufacturer Part Number
MC56F836
Description
56f8300 16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC56F8365MFGE
Manufacturer:
Freescale
Quantity:
278
Part Number:
MC56F8365MFGE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC56F8365VFGE
Manufacturer:
Freescale
Quantity:
619
Part Number:
MC56F8365VFGE
Manufacturer:
FREESCALE
Quantity:
125
Part Number:
MC56F8365VFGE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC56F8365VFGE
Manufacturer:
FREESCALE
Quantity:
125
Part Number:
MC56F8366MFV60
Manufacturer:
Power-one
Quantity:
268
Part Number:
MC56F8366MFVE
Manufacturer:
Freescale
Quantity:
440
Part Number:
MC56F8366MFVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC56F8366MFVE
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC56F8366VFV60
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC56F8366VFVE
Manufacturer:
Freescale
Quantity:
43
Part Number:
MC56F8366VFVE
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC56F8367MPYE
Manufacturer:
FREESCALE
Quantity:
20 000
5.2 Features
The ITCN module design includes these distinctive features:
For further information, see
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 86 interrupt
sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. Next, all of
the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the
active interrupt requests for that level. Within a given priority level, 0 is the highest priority, while number
85 is the lowest.
5.3.1
Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest
priority, an interrupt vector address is generated. Normal interrupt handling concatenates the VBA and the
vector number to determine the vector address. In this way, an offset is generated into the vector table for
each interrupt.
5.3.2
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be
serviced. The following tables define the nesting requirements for each priority level.
80
Programmable priority levels for each IRQ
Two programmable Fast Interrupts
Notification to SIM module to restart clocks out of Wait and Stop modes
Drives initial address on the address bus after reset
Normal Interrupt Handling
Interrupt Nesting
1. Core status register bits indicating current interrupt mask within the core.
SR[9]
0
0
1
1
IPIC_LEVEL[1:0]
1
00
01
Table
Table 5-2. Interrupt Priority Encoding
Table 5-1 Interrupt Mask Bit Definition
SR[8]
1
0
1
0
1
4-5, Interrupt Vector Table Contents.
1
No Interrupt or SWILP
Priority 0
56F8365 Technical Data, Rev. 7
Current Interrupt
Priority Level
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priorities 2, 3
Priority 3
Permitted Exceptions
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Exception Priority
Required Nested
None
Priority 0
Priorities 0, 1
Priorities 0, 1, 2
Masked Exceptions
Freescale Semiconductor
Preliminary

Related parts for MC56F836