HT56R66 Holtek Semiconductor Inc., HT56R66 Datasheet
HT56R66
Related parts for HT56R66
HT56R66 Summary of contents
Page 1
... The usual Holtek MCU features such as power down and wake-up functions, oscillator options, programmable frequency divider, etc. combine to ensure user applica- tions require a minimum of external components. 1 HT56R66/HT56R666 2 C September 8, 2009 ...
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... HT56R666 16K 16 1152 8 5.5V Note: 1. The devices are only available in OTP versions. 2. For devices that exist in more than one package formats, the table reflects the situation for the larger package. Block Diagram Rev. 1.10 HT56R66/HT56R666 Timer I/O LCD A/D 8-bit 16-bit 12-bit 8 12-bit 4 ...
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... Pin Assignment Rev. 1.10 HT56R66/HT56R666 3 September 8, 2009 ...
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... This 32768Hz crystal is disabled/enabled by configu- SUB SL ration option. A/D reference voltage input pin Schmitt Trigger reset input. Active low Positive power supply Negative power supply, ground Analog positive power supply Analog negative power supply, ground 4 HT56R66/HT56R666 September 8, 2009 ...
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... CMOS outputs using control bits in the LCD control registers. COM0~COM7 are the LCD common outputs. +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total.............................................................. 80mA OH 5 HT56R66/HT56R666 Bus 2 C Bus 2 C Bus 2 C Bus clock September 8, 2009 ...
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... I (Slow Mode, f =8MHz) DD12 M (Crystal OSC, RC OSC) Operating Current I (Slow Mode, f =8MHz) DD13 M (Crystal OSC, RC OSC) Operating Current I (f =32768Hz (note 1) DD14 SYS or 32K_INT internal RC OSC) Rev. 1.10 HT56R66/HT56R666 Test Conditions Min. V Conditions DD f =4MHz 2.2 SYS f =8MHz 3.0 SYS f =12MHz 4.5 SYS V =AV 3.0 REF ...
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... Input High Voltage for I/O Ports, V IH1 TMR and INT V Input Low Voltage (RES) IL2 V Input High Voltage (RES) IH2 V Low Voltage Reset Voltage LVR Rev. 1.10 HT56R66/HT56R666 Test Conditions Min. V Conditions DD No load, WDT off, 3V LCD on (note 2), R type LCD1 DD 5V ...
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... Buzzer, RTC Interrupt, Time Base Interrupt and the WDT Both Timer/Event Counters are off. Timer filter is disabled for all test conditions. 5. All peripherals are in OFF condition if not mentioned at I Rev. 1.10 HT56R66/HT56R666 Test Conditions Min. V Conditions DD Configuration option: 2 ...
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... Mode, f =8MHz) DD13 M (Crystal OSC, RC OSC) Operating Current I (f =32768Hz (note 1) DD14 SYS or 32K internal RC OSC) Operating Current I (f =32768Hz (note 1) DD15 SYS or 32K internal RC OSC) Rev. 1.10 HT56R66/HT56R666 Test Conditions Min. V Conditions DD f =4MHz 2.2 SYS f =8MHz 3.0 SYS f =12MHz 4.5 SYS V =AV 3 ...
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... On =4MHz, SYS SYS off; f (note 3)= STB9 WDT LCD S f =32768Hz (note 1) SUB or 32K RC OSC) Rev. 1.10 HT56R66/HT56R666 Test Conditions Min. V Conditions DD WDT off, LCD on (note 2), 3V 1/3 bias (R =600k ), BIAS LCD DD WDT off, LCD on (note 2), 3V 1/5 bias (R =100k ), BIAS ...
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... D.C. current measurement. 2. LCD waveform is in Type A condition internal clock for Buzzer, RTC, Time base and WDT Timer0/1 off. Timer filter disable in all test condition. 5. All peripherals are in OFF condition if not mentioned at I Rev. 1.10 HT56R66/HT56R666 Test Conditions Min. V Conditions DD 0 0.7V ...
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... System Start-up Timer Period SST1 System Start-up Timer Period for t SST2 XTAL or RTC oscillator System Start-up Timer Period for t SST3 External RC or External Clock t Interrupt Pulse Width INT Note: *t =1/f or 1/f SYS SYS1 SYS2 Rev. 1.10 HT56R66/HT56R666 Test Conditions Min. V Conditions DD 2.2V~5.5V 32 3.0V~5.5V 32 4.5V~5.5V 32 2.2V~5.5V 0 3.0V~5.5V 0 4.5V~5.5V 0 2.2V~5.5V, 28.8 After Trim 1 0 ...
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... V A/D Input Voltage AD A/D Input Reference Voltage V REF Range DNL A/C Differential Non-Linearity INL ADC Integral Non-Linearity Additional Power Consumption I ADC if A/D Converter is Used t A/D Clock Period AD t A/D Conversion Time ADC Rev. 1.10 HT56R66/HT56R666 Test Conditions Min. V Conditions DD 52QFP, 64LQFP 0 100QFP 0 AV =5V 1 =5V REF ...
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... Symbol Parameter VDD Start Voltage to Ensure V POR Power-on Reset VDD raising rate to Ensure RR VDD Power-on Reset Minimum Time for VDD Stays at t POR V to Ensure Power-on Reset POR Rev. 1.10 HT56R66/HT56R666 Test Conditions Min. V Conditions DD 0.035 1 14 Ta=25 C Typ. Max. Unit 100 mV V/ms ms ...
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... The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. System Clocking and Pipelining Instruction Fetching 15 HT56R66/HT56R666 /4 with a 1:3 high/low duty cycle. September 8, 2009 ...
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... Program Counter + 2 @6 #12 #11 # S12 S11 S10 Program Counter @7~@0: PCL bits S13~S0: Stack register bits 16 HT56R66/HT56R666 ...
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... Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA Rev. 1.10 HT56R66/HT56R666 Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC Increment and Decrement INCA, INC, DECA, DEC Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, ...
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... Any unused bits in this transferred higher order byte will be read The following diagram illustrates the addressing/data flow of the look-up table: Table Location Bits PC9 PC8 @ Table Location 18 HT56R66/HT56R666 September 8, 2009 ...
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... Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the HT56R666. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is 3F00H which re- fers to the start address of the last page within the 16K Program Memory of the HT56R666 microcontroller ...
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... Data Memory capacities. As the Special Purpose Data Memory registers are mapped into all bank areas, they can subsequently be accessed from any bank location. Data Memory Structure Common 00H Common 3FH Common 00H Common 3FH Data Memory Content 20 HT56R66/HT56R666 September 8, 2009 ...
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... I/O data control and A/D converter operation. The location of these registers within the Data Memory begins at the address 00H. Any unused Data Memory locations between these special Rev. 1.10 HT56R66/HT56R666 Special Purpose Data Memory 21 September 8, 2009 ...
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... The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. Rev. 1.10 HT56R66/HT56R666 dressing Registers indirectly will return a result of 00H and writing to the registers indirectly will result in no op- eration. Memory Pointers - MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are pro- vided ...
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... Loading a value directly into this PCL register will cause a jump to the specified Program Memory lo- Rev. 1.10 HT56R66/HT56R666 cation, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are per- mitted. When such operations are used, note that a dummy cycle will be inserted ...
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... The registers TMR0, TMR1, TMR2, TMR3 and the register pair TMR1L/TMR1H are the locations where the timer values are located. These Rev. 1.10 HT56R66/HT56R666 Status Register registers can also be preloaded with fixed data to allow different time intervals to be setup. The associated ...
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... The four lower bits are used for the Watchdog Timer control, while the highest four bits are used to se- lect open drain outputs for pins PA0~PA3. Rev. 1.10 HT56R66/HT56R666 Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of ev- ...
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... PA0~PA3 Open Drain Control - MISC Rev. 1.10 Generic Input/Output Structure A/D Input/Output Structure 26 HT56R66/HT56R666 September 8, 2009 ...
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... Note that the original I/O function will remain even if the pin is setup to be used as an external timer input. Rev. 1.10 HT56R66/HT56R666 PFD Output The device contains a PFD function whose single out- put is pin-shared with I/O pin PA3. The output function of this pin is chosen via a configuration option and re- mains fixed after the device is programmed ...
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... HT56R666 or 1/ 1/5 LCD Selections Device LED Duty Static 1/4 HT56R666 1/8 1/12 1/16 LED Selections Note: The HT56R66 device do not have an LED driver function. 28 Bias Wave Type Type LED Driver No September 8, 2009 ...
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... R Type Bias Voltage Levels - HT56R66 R Type Bias Voltage Levels - HT56R666 Rev. 1.10 C Type Bias Voltage Levels 29 HT56R66/HT56R666 September 8, 2009 ...
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... The accompanying Display Memory Map diagrams shows how the internal Display Memory is mapped to the Segments and Commons of the display for the larg- est device, which is the HT56R666. Display Memory Maps for devices with smaller memory capacities can be extrapolated from these diagrams. ...
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... LCD driver, as well as its biasing and duty selections, are dependent upon how the LCD control bits are pro- grammed. The Bias Type, whether type is se- lected using a configuration option. Only HT56R66 is with type selection configuration option. If the C-type of bias is used when an internal charge pump will be enabled ...
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... LCD Control Register - LCDCTRL - HT56R66 LCD Control Register - LCDCTRL - HT56R666 Rev. 1.10 HT56R66/HT56R666 32 September 8, 2009 ...
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... LED Control Register - LEDCTRL - HT56R666 LCD Output Control Register - LCDOUT1 LCD Output Control Register - LCDOUT2 Rev. 1.10 HT56R66/HT56R666 33 September 8, 2009 ...
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... VLCD1 pin then the VMAX pin should be connected to VDD, otherwise the VMAX pin should be connected to pin VLCD1. Note that no exter- nal capacitors or resistors are required to be connected if R type biasing is used. Rev. 1.10 HT56R66/HT56R666 Condition VMAX connection VDD > VLCD1 Connect VMAX to VDD Otherwise ...
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... LED 1/4 Duty, COM High Active, SEG Low Active, Display Off LED Static Mode Normal Operation Rev. 1.10 HT56R66/HT56R666 Programming Considerations Certain precautions must be taken when programming the LCD/LED. One of these is to ensure that the Display Memory is properly initialised after the microcontroller is powered on. Like the General Purpose Data Memory, the contents of the Display Memory are in an unknown condition after power-on ...
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... LED 1/4 Duty, COM High Active, SEG Low Active, Normal Operation Note: For 1/2 Bias, VA=VLCD1, VB=VLCD1 1/2 for both R and C type. LCD Driver Output - Type A - 1/2 Duty, 1/2 Bias Rev. 1.10 HT56R66/HT56R666 36 September 8, 2009 ...
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... Note: For 1/2 Bias, the VA=VLCD1, VB=VLCD1 1/2 for both R and C type. LCD Driver Output - Type A- 1/3 Duty, 1/2 Bias Rev. 1.10 HT56R66/HT56R666 37 September 8, 2009 ...
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... Note: For 1/3 R type bias, the VA=VLCD1, VB=VLCD1 2/3 and VC=VLCD1 1/3. For 1/3 C type bias, the VA=VLCD1 1.5, VB=VLCD1 and VC=VLCD1 1/2. LCD Driver Output - Type A - 1/4 Duty, 1/3 Bias Rev. 1.10 HT56R66/HT56R666 38 September 8, 2009 ...
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... Note: For 1/3 R type bias, the VA=VLCD1, VB=VLCD1 2/3 and VC=VLCD1 1/3. For 1/3 C type bias, the VA=VLCD1 1.5, VB=VLCD1 and VC=VLCD1 1/2. LCD Driver Output - Type A - 1/3 Duty, 1/3 Bias Rev. 1.10 HT56R66/HT56R666 39 September 8, 2009 ...
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... In addition, their clock source can also be configured to come from an external timer pin. Rev. 1.10 HT56R66/HT56R666 Configuring the Timer/Event Counter Input Clock Source The internal timer s clock can originate from various sources. The system clock source is used when the Timer/Event Counter is in the timer mode or in the pulse width measurement mode ...
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... Rev. 1.10 HT56R66/HT56R666 The actual transfer of the data into the low byte timer register is only carried out when a write to its associated high byte timer register, namely TMR1H, is executed. ...
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... Timer/Event Counter Structure 16-bit Timer/Event Counter Structure Timer/Event Counter Control Register - TMRnC Rev. 1.10 HT56R66/HT56R666 42 September 8, 2009 ...
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... Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the corre- sponding Interrupt Control Register, is reset to zero. Timer Mode Timing Chart 43 HT56R66/HT56R666 Bit7 Bit6 0 1 September 8, 2009 ...
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... The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is re- set to zero. As the external timer pin is shared with an I/O pin, to en- sure that the pin is configured to operate as a pulse Event Counter Mode Timing Chart 44 HT56R66/HT56R666 September 8, 2009 ...
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... Using this method of frequency generation, and if a crystal oscillator is used for the system clock, very pre- cise values of frequency can be generated. Rev. 1.10 HT56R66/HT56R666 Bits TnPSC0~TnPSC2 of the control register can be used to define the pre-scaling stages of the internal clock source of the Timer/Event Counter. The Timer/Event Counter overflow signal can be used to generate signals for the PFD and Timer Interrupt ...
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... Timer/Event Counter 0 - note mode bits must be previously setup Rev. 1.10 HT56R66/HT56R666 isters are unknown. After the timer has been initialised the timer can be turned on and off by controlling the en- able bit in the timer control register. Note that setting the ...
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... PWM function, but a 1 has been written to Duty its corresponding bit in the PDC control register to con- figure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor selections. 47 HT56R66/HT56R666 AC (0~15) DC (Duty Cycle) DC 256 ...
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... PWM0L register value clr pdc.0 ; setup pin PD0 as an output set pwm0en ; set the PWM0 enable bit set pd.0 ; Enable the PWM0 output : : : : clr pd.0 ; PWM0 output disabled Rev. 1.10 HT56R66/HT56R666 PD0 will remain low 8+4 PWM Mode PWM Register Pairs 48 September 8, 2009 ...
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... AN0~AN7 will all be set as analog in- puts. Note that if the PCR2~PCR0 bits are all set to zero, then all the Port B pins will be setup as normal I/Os and the internal A/D converter circuitry will be powered off to reduce the power consumption. A/D Converter Structure 49 HT56R66/HT56R666 Bit Bit Bit Bit Bit Bit ...
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... ADCS2, ADCS1 and ADCS0 bits in the ACSR register. Rev. 1.10 HT56R66/HT56R666 Controlling the on/off function of the A/D converter cir- cuitry is implemented using the ADONB bit in the ACSR register and the value of the PCR bits in the ADCR reg- ister ...
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... Select which pins on Port B are to be used as A/D in- puts and configure them as A/D input pins by correctly programming the PCR2~PCR0 bits in the ADCR reg- ister. Note that this step can be combined with Step 2 into a single ADCR register programming operation. 51 HT56R66/HT56R666 ADCS2, ADCS1, ADCS0=011 Undefined Undefined Undefined ...
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... A/D converter. After an A/D conversion process has been initiated by the application program, the microcontroller Rev. 1.10 HT56R66/HT56R666 A/D Conversion Timing internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16t where t is equal to the A/D clock period ...
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... STATUS from user defined memory ; restore ACC from user defined memory ; clear ADC interrupt flag 53 HT56R66/HT56R666 September 8, 2009 ...
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... SCS pin only one slave device can be utilised. The SPI function in this device offers the following fea- tures: Full duplex synchronous data transfer Both Master and Slave modes LSB first or MSB first data transmission modes Transmission complete flag 54 HT56R66/HT56R666 September 8, 2009 ...
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... H: CKPOL=0 SCK Z L: CKPOL=1 Note: Z floating, H output high, L output low, I Input, O output level, I,Z input floating (no pull-high) Rev. 1.10 HT56R66/HT56R666 Configuration Option SIM Function SPI CSEN bit SPI WCOL bit SPI Interface Configuration Options SPI Registers There are three internal registers which control the over- all operation of the SPI interface ...
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... SPI/I Rev. 1. Control Register - SIMCTL0 C Control Register - SIMCTL1 2 I SPI Control Register - SIMCTL2 56 HT56R66/HT56R666 September 8, 2009 ...
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... SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the Timer/Event Counter. If Rev. 1.10 HT56R66/HT56R666 the SPI Slave Mode is selected then the clock will be supplied by an external Master device. SIM0 ...
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... Rev. 1.10 SPI Master Mode Timing SPI Slave Mode Timing (CKEG=0) SPI Slave Mode Timing (CKEG=1) 58 HT56R66/HT56R666 September 8, 2009 ...
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... Rev. 1.10 SPI Transfer Control Flowchart 59 HT56R66/HT56R666 September 8, 2009 ...
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... I bus, the slave transmit mode and the slave receive mode. Rev. 1.10 HT56R66/HT56R666 There are several configuration options associated 2 with the I C interface. One of these is to enable the function which selects the SIM pins rather than normal I/O pins ...
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... The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon com- pletion of an 8-bit data transfer the flag will go high and an interrupt will be generated. 61 HT56R66/HT56R666 2 C bus. When the 2 C busy flag. This flag will be ...
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... SIMDR register the receive mode where it must implement a dummy read from the SIMDR regis- ter to release the SCL line. C Slave Address Register - SIMAR 62 HT56R66/HT56R666 2 C bus and not by the 2 C bus. To deter- September 8, 2009 ...
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... I Rev. 1.10 C Communication Timing Diagram Bus ISR Flow Chart 63 HT56R66/HT56R666 September 8, 2009 ...
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... Clock, clearing it disables it. The required division ratio of the system clock is selected using the PCKPSC0 and PCKPSC1 bits in the same register. If the system enters the Sleep Mode this will disable the Peripheral Clock output. Peripheral Clock Block Diagram 64 HT56R66/HT56R666 clock. SYS September 8, 2009 ...
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... S that generates f , which in turn controls the buzzer fre- S quency, can originate from three different sources, the Rev. 1.10 HT56R66/HT56R666 32768Hz oscillator, the 32K_INT oscillator or the Sys- tem oscillator/4, the choice of which is determined by the f clock source configuration option. Note that the S buzzer frequency is controlled by configuration options, ...
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... Buzzer Output Pin Control 66 HT56R66/HT56R666 Output Function PA0=BZ PA1=BZ PA0= 0 PA1= 0 ...
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... This will prevent any further interrupt nesting from occurring. However, if other interrupt requests oc- cur during this interval, although the interrupt will not be Rev. 1.10 HT56R66/HT56R666 immediately serviced, the request flag will still be re- corded interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the rou- tine, to allow interrupt nesting ...
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... Interrupt Control Register - INTC0 Interrupt Control Register - INTC1 Rev. 1.10 HT56R66/HT56R666 68 September 8, 2009 ...
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... Interrupt Control Register - MFIC/MFIC0 Interrupt Control Register - MFIC1 Rev. 1.10 HT56R66/HT56R666 69 September 8, 2009 ...
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... The external interrupt pins are connected to an internal filter to reduce the possibility of unwanted external inter- rupts due to adverse noise or spikes on the external in- Rev. 1.10 HT56R66/HT56R666 Interrupt Structure terrupt input signal. As this internal filter circuit will consume a limited amount of power, a configuration op- tion is provided to switch off the filter function, an option which may be beneficial in power sensitive applications, but in which the integrity of the input signal is high ...
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... Timer/Event Counter 2 or Timer/Event counter 3 overflows. When the interrupt is enabled, the stack is not full and the Timer/Event Rev. 1.10 HT56R66/HT56R666 Counter 2 or Timer/Event counter 3 overflows, a subrou- tine call to the Multi-function interrupt vector at location 18H, will take place. When the Timer/Event 2 or ...
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... Timer 2 or Timer 3 overflow interrupt will not be automatically reset and must be manually reset by the application program. Real Time Clock Control Register - RTCC Rev. 1.10 HT56R66/HT56R666 Real Time Clock Interrupt The Real Time Clock Interrupt is contained within the Multi-function Interrupt. For a Real Time Clock interrupt to be generated, the ...
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... Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of re- set operations result in different register conditions be- ing setup. Time Base Interrupt 73 HT56R66/HT56R666 September 8, 2009 ...
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... Reset Circuit shown is recommended. More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website. Rev. 1.10 HT56R66/HT56R666 Note recommended that this component is added for added ESD protection ** It is recommended that this component is added in environments where power line noise ...
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... SST WDT Time-out Reset during Power Down Timing Chart Rev. 1.10 HT56R66/HT56R666 Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer ...
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... PWM2L PWM2H PWM3L Rev. 1.10 HT56R66/HT56R666 RES Reset WDT Time-out (Normal Operation) (Normal Operation ...
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... SIMDR SIMAR/SIMCTL2 Note: u stands for unchanged x stands for unknown stands for unimplemented Rev. 1.10 HT56R66/HT56R666 RES Reset WDT Time-out (Normal Operation) (Normal Operation ...
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... MHz. More information regarding oscillator applications is lo- cated on the Holtek website. Crystal/Ceramic Oscillator Rev. 1.10 HT56R66/HT56R666 Crystal Oscillator C1 and C2 Values Crystal Frequency 12MHz 8MHz 4MHz 1MHz 455kHz (see Note 2) Note: 1 ...
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... CLKMOD register. External 32768Hz Oscillator Rev. 1.10 HT56R66/HT56R666 During power-up there is a time delay associated with the 32768Hz oscillator waiting for it to start-up. To mini- mise this time delay, bit 4 of the RTCC register, known as the QOSC bit, is provided to have a quick start-up function ...
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... CLKMOD register to provide the low fre- quency clock source f . SLOW Clock Control Register - CLKMOD Rev. 1.10 HT56R66/HT56R666 An additional sub internal clock, with the internal name 32kHz clock source which can be sourced from SUB either the internal 32K_INT oscillator or an external 32768 Hz crystal, selected by configuration option ...
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... Rev. 1.10 Dual Clock Mode Operation Dual Clock Mode Structure 81 HT56R66/HT56R666 September 8, 2009 ...
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... The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place interrupt request flag is set to 1 be- 82 HT56R66/HT56R666 September 8, 2009 ...
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... LVDC bit in the RTCC register to zero. Note that if the LVD is enabled there will be some power Rev. 1.10 HT56R66/HT56R666 consumption associated with its internal circuitry, how- ever, by clearing the LVDC bit to zero the power can be minimised important not to confuse the LVD with the LVR function ...
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... CLR WDT2 instruction will clear the Watchdog Timer. Similarly after the CLR WDT2 instruction has been executed, only a successive CLR WDT1 instruction can clear the Watchdog Timer. 84 HT56R66/HT56R666 September 8, 2009 ...
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... Buzzer frequency Time Base Option 10 Time base time-out period: 2 LCD Option 11 LCD type HT56R66 only Watchdog Options 12 Watchdog Timer function: enable or disable 13 CLRWDT instructions instructions 12 14 WDT time-out period LVD/LVR Options 15 LVD function: enable or disable ...
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... External peripheral interrupt or Segment function Timer/Event Counter and External Interrupt Pins Filter Option 23 Interrupt and Timer/Event Counter input pins internal filter On/Off control Lock Options 24 Lock All 25 Partial Lock Application Circuits Application Circuit for HT56R66 Rev. 1.10 HT56R66/HT56R666 Options applies to all pins 86 September 8, 2009 ...
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... Application Circuit for HT56R666 Rev. 1.10 HT56R66/HT56R666 87 September 8, 2009 ...
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... Care must be taken to en- Rev. 1.10 HT56R66/HT56R666 sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for sub- traction. The increment and decrement instructions ...
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... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 1.10 HT56R66/HT56R666 Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.10 HT56R66/HT56R666 Description 90 Cycles Flag Affected ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.10 HT56R66/HT56R666 91 September 8, 2009 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.10 HT56R66/HT56R666 addr 92 September 8, 2009 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT56R66/HT56R666 September 8, 2009 ...
Page 94
... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.10 HT56R66/HT56R666 addr 94 September 8, 2009 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.10 Stack Stack Stack [m]. 0~6) 95 HT56R66/HT56R666 September 8, 2009 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.10 [m]. 0~6) 96 HT56R66/HT56R666 September 8, 2009 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.10 [ HT56R66/HT56R666 September 8, 2009 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.10 0 [m] [ HT56R66/HT56R666 September 8, 2009 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.10 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 99 HT56R66/HT56R666 September 8, 2009 ...
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... Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.10 HT56R66/HT56R666 100 September 8, 2009 ...
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... Package Information 52-pin QFP (14mm´14mm) Outline Dimensions Symbol Rev. 1.10 Dimensions in mm Min. Nom. 17.30 13.90 17.30 13.90 1.00 0.40 2.50 0.10 0.73 0.10 0 101 HT56R66/HT56R666 Max. 17.50 14.10 17.50 14.10 3.10 3.40 1.03 0.20 7 September 8, 2009 ...
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... LQFP (7mm´7mm) Outline Dimensions Symbol Rev. 1.10 Dimensions in mm Min. Nom. 8.90 6.90 8.90 6.90 0.40 0.13 1.35 0.05 0.45 0.09 0 102 HT56R66/HT56R666 Max. 9.10 7.10 9.10 7.10 0.23 1.45 1.60 0.15 0.75 0.20 7 September 8, 2009 ...
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... QFP (14mm´20mm) Outline Dimensions Symbol Rev. 1.10 Dimensions in mm Min. Nom. 18.50 13.90 24.50 19.90 0.65 0.30 2.50 0.10 1.00 0.10 0 103 HT56R66/HT56R666 Max. 19.20 14.10 25.20 20.10 3.10 3.40 1.40 0.20 7 September 8, 2009 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 HT56R66/HT56R666 104 September 8, 2009 ...