HT56R66 Holtek Semiconductor Inc., HT56R66 Datasheet - Page 60

• Manufacturer Part Number: HT56R66
• Description: Tinypower Tm A/d Type With Lcd 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

SPI Communication
After the SPI interface is enabled by setting the SIMEN
bit high, then in the Master Mode, when data is written to
the SIMDR register, transmission/reception will begin si-
multaneously. When the data transfer is complete, the
TRF flag will be set automatically, but must be cleared
using the application program. In the Slave Mode, when
the clock signal from the master has been received, any
data in the SIMDR register will be transmitted and any
data on the SDI pin will be shifted into the SIMDR regis-
ter. The master should output an SCS signal to enable
the slave device before a clock signal is provided and
slave data transfers should be enabled/disabled be-
fore/after an SCS signal is received.
The SPI will continue to function even after a HALT in-
struction has been executed.
I
The I
peripheral devices such as sensors, EEPROM memory
etc. Originally developed by Philips, it is a two line low
speed serial interface for synchronous serial data trans-
fer. The advantage of only two lines for communication,
relatively simple communication protocol and the ability
to accommodate multiple devices on the same bus has
made it an extremely popular interface type for many
applications.
Rev. 1.10
2
C Interface
I
The I
data line, SDA, and serial clock line, SCL. As many
devices may be connected together on the same bus,
their outputs are both open drain types. For this rea-
son it is necessary that external pull-high resistors are
connected to these outputs. Note that no chip select
line exists, as each device on the I
by a unique address which will be transmitted and re-
ceived on the I
When two devices communicate with each other on
the bidirectional I
device and one as the slave device. Both master and
slave can transmit and receive data, however, it is the
master device that has overall control of the bus. For
these devices, which only operates in slave mode,
there are two methods of transferring data on the I
bus, the slave transmit mode and the slave receive
mode.
CKPOL
2
C Interface Operation
2
0
0
1
1
C interface is used to communicate with external
2
C serial interface is a two line interface, a serial
CKEG
2
C bus.
0
1
0
1
2
C bus, one is known as the master
Active Falling Edge
Active Falling Edge
Active Rising Edge
Active Rising Edge
SCK Clock Signal
High Base Level
High Base Level
Low Base Level
Low Base Level
2
C bus is identified
2
C
60
There are several configuration options associated
with the I
function which selects the SIM pins rather than normal
I/O pins. Note that if the configuration option does not
select the SIM function then the SIMEN bit in the
SIMCTL0 register will have no effect. A configuration
option exists to allow a clock other than the system
clock to drive the I
option determines the debounce time of the I
face. This uses the internal clock to in effect add a
debounce time to the external clock to reduce the pos-
sibility of glitches on the clock line causing erroneous
operation. The debounce time, if selected, can be
chosen to be either 1 or 2 system clocks.
I
There are three control registers associated with the
I
data register, SIMDR. The SIMDR register, which is
shown in the above SPI section, is used to store the
data being transmitted and received on the I
Before the microcontroller writes data to the I
the actual data to be transmitted must be placed in the
SIMDR register. After the data is received from the I
bus, the microcontroller can read it from the SIMDR
register. Any transmission or reception of data from
the I
Note that the SIMAR register also has the name
SIMCTL2 which is used by the SPI function. Bits
SIMIDLE , SIMEN and bits SIM0~SIM2 in register
SIMCTL0 are used by the I
register is shown in the above SPI section.
2
2
C Registers
C bus, SIMCTL0, SIMCTL1 and SIMAR and one
SIM function
I
I
2
2
C clock
C debounce
2
C bus must be made via the SIMDR register.
I
2
C Interface Configuration Options
SIM
2
C interface. One of these is to enable the
2
C interface. Another configuration
SIM interface or SEG pins
I
Disable/Enable
No debounce, 1 system clock;
2 system clocks
HT56R66/HT56R666
2
C runs without internal clock
2
C interface. The SIMCTL0
Function
September 8, 2009
2
2
C inter-
2
C bus.
C bus,
2
C