HT56R66 Holtek Semiconductor Inc., HT56R66 Datasheet - Page 45

• Manufacturer Part Number: HT56R66
• Description: Tinypower Tm A/d Type With Lcd 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

width measurement pin, two things have to happen. The
first is to ensure that the Operating Mode Select bits in
the Timer Control Register place the Timer/Event Coun-
ter in the Pulse Width Measurement Mode, the second
is to ensure that the port control register configures the
pin as an input.
Programmable Frequency Divider - PFD
The Programmable Frequency Divider provides a
means of producing a variable frequency output suitable
for applications requiring a precise frequency generator.
The PFD output is pin-shared with the I/O pin PA3. The
PFD function is selected via configuration option, how-
ever, if not selected, the pin can operate as a normal I/O
pin.
The clock source for the PFD circuit can originate from
either Timer/Event Counter 0 or Timer/Event Counter 1
overflow signal selected via configuration option. The
output frequency is controlled by loading the required
values into the timer registers and prescaler registers to
give the required division ratio. The timer will begin to
count-up from this preload register value until full, at
which point an overflow signal is generated, causing the
PFD output to change state. The timer will then be auto-
matically reloaded with the preload register value and
continue counting-up.
For the PFD output to function, it is essential that the corre-
sponding bit of the Port A control register PAC bit 3 is setup
as an output. If setup as an input the PFD output will not
function, however, the pin can still be used as a normal in-
put pin. The PFD output will only be activated if bit PA3 is
set to 1 . This output data bit is used as the on/off control
bit for the PFD output. Note that the PFD output will be low
if the PA3 output data bit is cleared to 0 .
Using this method of frequency generation, and if a
crystal oscillator is used for the system clock, very pre-
cise values of frequency can be generated.
Rev. 1.10
PFD Output Control
45
Bits TnPSC0~TnPSC2 of the control register can be
used to define the pre-scaling stages of the internal
clock source of the Timer/Event Counter. The
Timer/Event Counter overflow signal can be used to
generate signals for the PFD and Timer Interrupt.
I/O Interfacing
The Timer/Event Counter, when configured to run in the
event counter or pulse width measurement mode, re-
quire the use of external pins for correct operation. As
these pins are shared pins they must be configured cor-
rectly to ensure they are setup for use as Timer/Event
Counter inputs and not as a normal I/O pins. This is im-
plemented by ensuring that the mode select bits in the
Timer/Event Counter control register, select either the
event counter or pulse width measurement mode. Addi-
tionally the Port Control Register must be set high to en-
sure that the pin is setup as an input. Any pull-high
resistor on these pins will remain valid even if the pin is
used as a Timer/Event Counter input.
Timer/Event Counter Pins Internal Filter
The external Timer/Event Counter pins are connected to
an internal filter to reduce the possibility of unwanted
event counting events or inaccurate pulse width mea-
surements due to adverse noise or spikes on the exter-
nal Timer/Event Counter input signal. As this internal
filter circuit will consume a limited amount of power, a
configuration option is provided to switch off the filter
function, an option which may be beneficial in power
sensitive applications, but in which the integrity of the in-
put signal is high. Care must be taken when using the fil-
ter on/off configuration option as it will be applied not
only to both external Timer/Event Counter pins but also
to the external interrupt input pins. Individual
Timer/Event Counter or external interrupt pins cannot
be selected to have a filter on/off function.
HT56R66/HT56R666
September 8, 2009