ETC5054 STMicroelectronics, ETC5054 Datasheet

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ETC5054

Manufacturer Part Number
ETC5054
Description
Serial Interface Codec/filter
Manufacturer
STMicroelectronics
Datasheet

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DESCRIPTION
The ETC5057/ETC5054 family consists of A-law
and –law monolithic PCM CODEC/filters utilizing
the A/D and D/A conversion architecture shown in
the block diagram below, and a serial PCM inter-
face. The devices are fabricated using double-
poly CMOS process. The encode portion of each
device consists of an input gain adjust amplifier,
an active RC pre-filter which eliminates very high
frequency noise prior to entering a switched-ca-
pacitor band-pass filter that rejects signals below
200 Hz and above 3400 Hz. Also included are
auto-zero circuitry and a companding coder which
samples the filtered signal and encodes it in the
companded A-law or –law PCM format. The de-
code portion of each device consists of an ex-
panding decoder, which reconstructs the analog
signal from the companded A-law or –law code,
a low-pass filter which corrects for the sin x/x re-
sponse of the decoder output and rejects signals
above 3400 Hz and is followed by a single-ended
power amplifier capable of driving low impedance
loads. The devices require 1.536 MHz, 1.544
March 2000
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
TEM (DEVICE) INCLUDING:
– Transmit high-pass and low-pass filtering.
– Receive low-pass filter with sin x/x correction.
– Active RC noise filters
– -law or A-law compatible COder and DECoder.
– Internal precision voltage reference.
– Serial I/O interface.
– Internal auto-zero circuitry.
(ETC5054FN, 20 PINS)
CCITT SPECIFICATIONS
mW
CALLY 3 mW
TERFACES
CUIT DENSITY
COMPLETE CODEC AND FILTERING SYS-
A-LAW 16 PINS (ETC5057FN, 20 PINS)
MEETS OR EXCEEDS ALL D3/D4 AND
LOW OPERATING POWER - TYPICALLY 60
POWER-DOWN STANDBY MODE - TYPI-
AUTOMATIC POWER-DOWN
TTL OR CMOS COMPATIBLE DIGITAL IN-
MAXIMIZES LINE INTERFACE CARD CIR-
0 to 70 C OPERATION
-LAW WITHOUT SIGNALING, 16 PINS
5V OPERATION
SERIAL INTERFACE CODEC/FILTER
MHz, or 2.048 MHz transmit and receive master
clocks, which may be asynchronous, transmit and
receive bit clocks which may vary from 64 kHz to
2.048 MHz, and transmit and receive frame sync
pulses. The timing of the frame sync pulses and
PCM data is compatible with both industry stand-
ard formats.
ORDERING NUMBERS:
ORDERING NUMBERS:
ORDERING NUMBERS:
DIP16 (Plastic)
SO16 (Wide)
ETC5057FN
ETC5054FN
ETC5057D
ETC5054D
ETC5057N
ETC5054N
PLCC20
ETC5054
ETC5057
1/18

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ETC5054 Summary of contents

Page 1

... MAXIMIZES LINE INTERFACE CARD CIR- CUIT DENSITY OPERATION DESCRIPTION The ETC5057/ETC5054 family consists of A-law and –law monolithic PCM CODEC/filters utilizing the A/D and D/A conversion architecture shown in the block diagram below, and a serial PCM inter- face. The devices are fabricated using double- poly CMOS process ...

Page 2

... ETC5054 - ETC5057 PIN CONNECTIONS (Top view) DIP and SO BLOCK DIAGRAM 2/18 PLCC ...

Page 3

... Open drain output which pulses low during the encoder time slot. Recommended to be grounded if not used. Gain Set Analog output of the transmit input amplifier. Used to set gain externally. Inverting Input of the Transmit Input Amplifier. Input Non-inverting Input of the Transmit Input Amplifier. Input ETC5054 - ETC5057 . following the FS leading R R leading edge ...

Page 4

... For asynchronous operation, separate transmit and receive clocks may be applied, MCLK R MCLK must be 2.048 MHz for the ETC5057 1.536 MHz, 1.544 MHz for the ETC5054, and need not be synchronous. For best transmission performance, however, MCLK chronous with MCLK , which is easily achieved X ...

Page 5

... The output of this filter directly drives the en- coder sample-and-hold circuit. The A com- panding type according to A-law (ETC5057) or – law (ETC5054) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload ( nominally 2.5V MAX peak (see table of transmission characteristics) ...

Page 6

... ETC5054 - ETC5057 ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (all devices) Symbol Parameter I XA Input Leakage Current I (–2.5V V +2.5V Input Resistance I (–2.5V V +2.5V Output Resistance (closed loop, unity gain Load Resistance Load Capacitance Output Dynamic Range (R 10K ) Voltage Gain (VF ...

Page 7

... 100 BCLK , whichever comes later low. 50 R/X invalid Low 80 X/R Low 100 X/R 160 ETC5054 - ETC5057 Typ. Max. Unit 1.536 MHz 1.544 MHz 2.048 MHz 488 15.725 165 ns 180 ...

Page 8

... ETC5054 - ETC5057 Figure 2: Short Frame Sync Timing 8/18 ...

Page 9

... Figure 3: Long Frame Sync Timing ETC5054 - ETC5057 9/18 ...

Page 10

... ETC5054 - ETC5057 TRANSMISSION CHARACTERISTICS +5V 5 –5V 5%, GNDA = 0V 1.0KHz amplifier connected for unity-gain non-inverting (unless otherwise specified). AMPLITUDE RESPONSE Symbol Parameter Absolute levels - nominal 0 dBm0 level is 4 dBm (600 ) 0 dBm0 t Max Overload Level MAX 3.14 dBm0 (A LAW) 3 ...

Page 11

... Min. – 40 – 30 Min LAW (VFXI = 5 100mVrms 100mVrms ETC5054 - ETC5057 Typ. Max. Unit 290 315 s 195 220 120 145 105 130 155 180 200 s – 25 – 20 ...

Page 12

... ETC5054 - ETC5057 TRANSMISSION CHARACTERISTICS (continued) NOISE (continued) Symbol Parameter SOS Spurius out-of-band Signals at the Channel Output Loop around measurement, 0dBm0, 300Hz - 3400Hz input applied to DR, measure individual image signals at DX 4600Hz - 7600Hz 7600Hz - 8400Hz 8400Hz - 100,000Hz DISTORTION Symbol Parameter STD ...

Page 13

... ETC5054 - ETC5057 a ETC505X family 2.5V is re- –pad at the out- to 319 R3 R4 3.5 52k 6.9 26k 10.4 17.4k 13.8 13k 17.3 10.5k 21.3 8.7k 24.2 7.5k 27.7 6.5k 31.1 5.8k 34.6 5.2k 70 2.6k 107 1.8k 144 1.3k 183 1.1k 224 ...

Page 14

... ETC5054 - ETC5057 Figure 6: Typical Synchronous Application. 14/18 ...

Page 15

... TYP. A 2.35 2.65 0.093 A1 0.1 0.3 0.004 B 0.33 0.51 0.013 C 0.23 0.32 0.009 D 10.1 10.5 0.398 E 7.4 7.6 0.291 e 1.27 0.050 H 10 10.65 0.394 h 0.25 0.75 0.010 L 0.4 1.27 0.016 K 0 (min.)8 (max ETC5054 - ETC5057 OUTLINE AND MECHANICAL DATA MAX. 0.104 0.012 0.020 0.013 0.413 0.299 0.419 0.030 0.050 SO16 Wide 15/18 ...

Page 16

... ETC5054 - ETC5057 mm inch DIM. MIN. TYP. MAX. MIN. TYP. a1 0.51 0.020 B 0.77 1.65 0.030 b 0.5 0.020 b1 0.25 0.010 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 I 5.1 L 3.3 0.130 Z 1.27 16/18 OUTLINE AND MECHANICAL DATA MAX. 0.065 0.787 0.280 0.201 DIP16 0.050 ...

Page 17

... E 7.37 8.38 0.290 e 1.27 0.050 F 0.38 0.015 G 0.101 M 1.27 0.050 M1 1.14 0.045 PLCC20ME OUTLINE AND MECHANICAL DATA MAX. 0.395 0.356 0.180 0.330 0.004 PLCC20 (Seating Plane Coplanarity) ETC5054 - ETC5057 17/18 ...

Page 18

... ETC5054 - ETC5057 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice ...

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