W90210F Winbond Electronics Corp America, W90210F Datasheet - Page 33

• Manufacturer Part Number: W90210F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

8.4 Serial I/O
8.4.1 UART Register Definition
0
0
1
0
1
2
The serial I/O megacell implements a full-duplex, bi-directional UART with FIFO.
3F8, DLAB = 0
3F8, DLAB = 0
3F9, DLAB = 0
3F8, DLAB = 1
3F9, DLAB = 1
3FA
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Peripheral
Interface
RBR[0:7]
THR[0:7]
IER[3:7]
DLL[0:7]
DLM[0:7]
IIR[0:7]
Control Register
Status Register
Output Buffer
Input Buffer.
Figure 8.8 Serial I/O with FIFO
Serial I/O megacell
33
Description
- Receiver Buffer Register.
- Read only.
- bit 7 is LSB.
- Transmitter Holding Register.
- Write only.
- bit 7 is LSB.
- Interrupt Enable Register.
* bit 7: Irpt_RDA enable (1/0- Enable/Disable).
* bit 6: Irpt_THRE enable (1/0- Enable/Disable).
* bit 5: Irpt_RLS enable (1/0- Enable/Disable).
* bit 4: Irpt_MOS enable (1/0- Enable/Disable).
- bit 3: Loop-back enable (1/0- Enable/Disable).
* Divisor Latch Register (LS).
* Divisor Latch Register (MS).
- Interrupt Ident. Register.
- Read only.
* bit 7: No Irpt pending (1/0- True/False).
* bit 6: Irpt ID bit (2).
* bit 5: Irpt ID bit (1).
* bit 4: Irpt ID bit (0).
- bit 3: DMA mode select (1/0- Mode 1/Mode 0).
- bit 2: RCVR trigger (LSB).
- bit 1: RCVR trigger (MSB).
- bit 0: FIFO mode enable (1/0- Enable/Disable).
Output Shift
Timing generator
Input Shift Reg.
Control Logic
Reg.
SIN
SOUT
OSC
W90210F
Version 1.4, 10/8/97