W90210F Winbond Electronics Corp America, W90210F Datasheet - Page 37

• Manufacturer Part Number: W90210F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

Bit [3]- ackIntEn
Bit [4]- SelectIn; is inverted and then driven as parallel prot nSelectIn (default 1).
Bit [5]- nInit; is driven as parallel port nInit (default 1).
Bit [6]- autofd; is inverted and then driven as parallel port nAutoFd (default 0).
Bit [7]- strobe; is inverted and then driven as parallel port nStrobe (default 0).
4. ECR register (offset 243) (R/W)
Bit[0:2]- mode (R/W)
Bit[3]- nErrIntrEn (R/W, Valid only in ECP mode)
Bit[4]- dmaEn (R/W)
Bit[5]- serviceIntr (R/W)
0
1: Enable an interrupt on the rising edge of nAck.
0: Disable the nAck interrupt (default)
In centronic peripheral mode, when the nAck is active, the bit will be cleared by hardware.
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Note that an interrupt pulse will be generated if nFault is asserted and this bit is written from a "1" to a
"0". This prevents interrupts from being lost in the time between the read of the ecr and the wrtie of the
ecr.
000: Standard parallel port mode (default).
001: PS/2 parallel port mode
010: Parallel port FIFO mode
011: ECP parallel port mode
100: Centronic peripheral mo de
101: Reserved
110: Test mode
111: Configuration mode
In Standard mode or Parallel FIFO mode, this bit is forced to 0. The drivers are enabled, i.e. the
data pins of the parallel port are always outputs. Otherwise, this bit tri-states the data output
drivers, so that data will be read from the peripheral.
In this mode, FIFO is reset and common collector drivers are used on the control lines (nStrobe,
nAutoFd, nInit, and nSelectIn). Direction bit is cleared to "0".
The direction could be forward or reverse. In reverse direction, reading the data register returns the
value on the data lines not the value in the data register.
This is the same as Standard parallel port mode except that Pwords are written or DMAed to the
FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that
this mode is only useful when the direction bit is 0.
In the forward direction, Pwords is placed into the FIFO and transmitted automatically to the
peripheral using ECP protocol. In the reverse direction, bytes are moved from the ECP data port
and packed into Pwords in the FIFO. All drivers have active pull-ups.
In this mode, the parallel port acts as a reverse port in centronics mode and the direction bit is
forced to 1. The nAutofd bit (DCR bit 6) is cleared, nAck is active until nAutofd bit (DCR bit 6) is
set to 1 by software. And the parallel port data will be latched in the data register.
In this mode, the FIFO may be read or written, but the data will not be transmitted on the parallel
port. Using this mode to test the depth of the FIFO, the write-threshold, and the read-threshold.
In this mode, the CNFGA and CNFGB registers are accessible at addresses 244 and 246
1: Disable the interrupt generated on the asserting edge of nFault (default).
0: Enables an interrupt pulse on the high to low edge of nFault.
1: Enables DMA, DMA starts when serviceIntr (bit 5) is 0.
0: Disables DMA unconditionally (default).
1: Disables DMA and all of the service interrupts (default).
0: Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has
occurred, serviceIntr bit shall be set to a "1" by the hardware. Writing this bit to a "1" will not cause
an interrupt.
case 1: dmaEn = 1
case 2: dmaEn = 0, direction = 0
case 3: dmaEn = 0, direction = 1
During DMA (this bit is set to a 1 when terminal count is reached)
This bit shall be set to 1 whenever there are writeIntrThreshold or more Pwords free in the
FIFO.
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W90210F
Version 1.4, 10/8/97