LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 102

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.12.2 Device Status Register (dsr)
BIT 3 nFault
BIT 4 Select
BIT 5 PError
BIT 6 nAck
BIT 7 nBusy
7.12.3 Device Control Register (dcr)
BIT 0 STROBE - STROBE
BIT 1 AUTOFD - AUTOFEED
BIT 2 nINIT - INITIATE OUTPUT
BIT 3 SELECTIN
BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
ADDRESS OFFSET = 01H
The Status Port is located at an offset of ‘01H’ from the base address. Bits0 - 2 are not implemented as
register bits, during a read of the Printer Status Register these bits are a low level. The bits of the Status
Port are defined as follows:
The level on the nFault input is read by the CPU as bit 3 of the Device Status Register.
The level on the Select input is read by the CPU as bit 4 of the Device Status Register.
The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status
Register.
The level on the nAck input is read by the CPU as bit 6 of the Device Status Register.
The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status Register.
ADDRESS OFFSET = 02H
The Control Register is located at an offset of ‘02H’ from the base address. The Control Register is
initialized to zero by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.
This bit is inverted and output onto the nSTROBE output.
This bit is inverted and output onto the nAutoFd output. A logic 1 causes the printer to generate a line feed
after each line is printed. A logic 0 means no autofeed.
This bit is output onto the nINITP output without inversion.
This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0
means the printer is not selected.
The interrupt request enable bit when set to a high level may be used to
from the Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description
of the interrupt under Operation, Interrupts.
DATASHEET
Page 102
enable interrupt requests
SMSC LPC47M172