LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 104

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.12.7 cnfgA (Configuration Register A)
7.12.8 cnfgB (Configuration Register B)
BIT 7 compress
BIT 6 intrValue
BIT [5:3] Parallel Port IRQ (read-only)
BITS [2:0] Parallel Port DMA (read-only)
7.12.9 ecr (Extended Control Register)
BITS 7,6,5
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte
at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold
has been reached.
Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example
if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order
as was written.
ADDRESS OFFSET = 400H
Mode = 111
This register is a read only register. When read, 10H is returned. This indicates to the system that this is an
8-bit implementation. (PWord = 1 byte)
ADDRESS OFFSET = 401H
Mode = 111
This bit is read only. During a read it is a low level. This means that this chip does not support hardware
RLE compression. It does support hardware de-compression.
Returns the value of the interrupt to determine possible conflicts.
to Table 7.7 - Programming for Configuration Register B (Bits 5:3)
to Table 7.8 - Programming for Configuration Register B (Bits 2:0)
ADDRESS OFFSET = 402H
Mode = all
This register controls the extended ECP parallel port functions.
These bits are Read/Write and select the Mode.
DATASHEET
Page 104
SMSC LPC47M172