LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 188

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Note 1 :
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
0x00
0x01
0x02
0x03
Config.
Port
LOGICAL
LOGICAL
NUMBER
NUMBER
DEVICE
DEVICE
This chip uses address bits [A11:A0] to decode the base address of each of its logical devices. Bit 6 of the
OSC Global Configuration Register (CR24) must be set to ‘1’ and Address Bits [A15:A12] must be ‘0’ for
16 bit address qualification.
FDC
Reserved
Serial Port 2
Parallel
Port
Config. Port
LOGICAL
LOGICAL
DEVICE
DEVICE
Table 11.8 - Logical Device I/O Address, LD_NUM Bit = 1
0x60,0x61
n/a
0x60,0x61
0x60,0x61
0x26, 0x27
REGISTER
REGISTER
INDEX
INDEX
DATASHEET
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
n/a
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
[0x0100:0x0FFC]
ON 4 BYTE BOUNDARIES
(EPP Not supported)
or
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
(all modes supported,
EPP is only available when
the base address is on an 8-
byte boundary)
0x0100:0x0FFE
On 2 byte boundaries
Page 188
BASE I/O
BASE I/O
(NOTE 1)
(NOTE 1)
RANGE
RANGE
+0 : SRA
+1 : SRB
+2 : DOR
+3 : TSR
+4 : MSR/DSR
+5 : FIFO
+7 : DIR/CCR
n/a
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
+0 : Data/ecpAfifo
+1 : Status
+2 : Control
+400h : cfifo/ecpDfifo/tfifo/cnfgA
+401h : cnfgB
+402h : ecr
+3 : EPP Address
+4 : EPP Data 0
+5 : EPP Data 1
+6 : EPP Data 2
+7 : EPP Data 3
See Configuration Register
Summary table. Accessed through
the index and DATA ports located at
the Configuration Port address and
the Configuration Port address +1
respectively.
BASE OFFSETS
BASE OFFSETS
FIXED
FIXED
SMSC LPC47M172