ADCLK846 Analog Devices, ADCLK846 Datasheet
ADCLK846
Available stocks
Related parts for ADCLK846
ADCLK846 Summary of contents
Page 1
... Medical and industrial imaging ATE and high performance instrumentation GENERAL DESCRIPTION The ADCLK846 is a 1.2 GHz/250 MHz, LVDS/CMOS, fanout buffer optimized for low jitter and low power operation. Possible configurations range from 6 LVDS to 12 CMOS outputs, including combinations of LVDS and CMOS outputs. Two control lines are used to determine whether fixed blocks of outputs are LVDS or CMOS outputs ...
Page 2
... Typical Performance Characteristics ..............................................8 Functional Description .................................................................. 11 Clock Inputs ................................................................................ 11 AC-Coupled Applications ......................................................... 11 Clock Outputs ............................................................................. 12 Control and Function Pins ........................................................ 12 Power Supply ............................................................................... 12 Applications Information .............................................................. 13 Using the ADCLK846 Outputs for ADC Clock Applications ................................................................................ 13 LVDS Clock Distribution .......................................................... 13 CMOS Clock Distribution ........................................................ 13 Input Termination Options ....................................................... 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15 Rev Page ...
Page 3
... Each pin (output shorted to GND ) Single-ended; termination = open OUTx and OUTx in phase MHz With 10 pF load each output; see Figure 16 for swing vs. frequency load load load load V ±500 μA Ω μA ADCLK846 ...
Page 4
... ADCLK846 www.DataSheet4U.com TIMING CHARACTERISTICS Table 2. Parameter LVDS OUTPUTS Output Rise/Fall Time Propagation Delay, CLK-to-LVDS Output Temperature Coefficient 1 Output Skew All LVDS Outputs on the Same Part All LVDS Outputs Across Multiple Parts Additive Time Jitter Integrated Random Jitter Broadband Random Jitter ...
Page 5
... PSR 0.9 ps/mV TPD PSR 1.2 ps/mV TPD Rev Page ADCLK846 Unit Conditions Input slew rate > 1 V/ns dBc/ offset dBc/Hz At 100 Hz offset dBc/ kHz offset dBc/ kHz offset dBc/Hz At 100 kHz offset dBc/ MHz offset dBc/ MHz offset Input slew rate > ...
Page 6
... ADCLK846 www.DataSheet4U.com ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Supply Voltage V to GND S Inputs CLK and CLK CMOS Inputs Outputs Maximum Voltage Voltage Reference Voltage (V ) REF Operating Temperature Range Ambient Junction Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ...
Page 7
... True Side of Differential LVDS Output 1, or CMOS Output 1 on Channel A. Complementary Side of Differential LVDS Output 0, or CMOS Output 0 on Channel B. True Side of Differential LVDS Output 0, or CMOS Output 0 on Channel A. Exposed Paddle. The exposed paddle must be connected to ground. Rev Page ADCLK846 ...
Page 8
... ADCLK846 www.DataSheet4U.com TYPICAL PERFORMANCE CHARACTERISTICS 25°C, unless otherwise noted CH2 100mV M 200ps 10.0GS/s Figure 3. LVDS Output Waveform at 1200 MHz 2.3 2.2 2.1 2.0 1.9 1.8 1.7 0.1 0.3 0.5 0.7 0.9 INPUT DIFFERENTIAL (V p-p) Figure 4. LVDS Propagation Delay vs 200 400 600 FREQUENCY (MHz) Figure 5. LVDS Output Duty Cycle vs. Frequency CH1 – ...
Page 9
... FREQUENCY (MHz) Figure 13. LVDS/CMOS Current vs. Frequency with Various Logic Combinations 100 150 FREQUENCY (MHz) Figure 14. CMOS Output Duty Cycle vs. Frequency Load ADCLK846 10M 100M 200 225 250 200 250 ...
Page 10
... ADCLK846 www.DataSheet4U.com 1 CH1 300mV 1.25ns/DIV Figure 15. CMOS Output Waveform at 200 MHz Load 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 50 100 150 FREQUENCY (MHz) Figure 16. CMOS Output Swing vs. Frequency and Temperature Load 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 100 FREQUENCY (MHz) Figure 17. CMOS Output Swing vs. Frequency and Capacitive Load CH1 954mV 25°C 85° ...
Page 11
... FUNCTIONAL DESCRIPTION The ADCLK846 clock input is distributed to all output channels. Each channel bank is pin programmable for either LVDS or CMOS levels. This allows the selection of multiple logic configurations ranging from 6 LVDS to 12 CMOS outputs, along with other combinations using both types of logic. ...
Page 12
... This pin has a 200 kΩ pull-down resistor. The control pins are operational during sleep mode. POWER SUPPLY The ADCLK846 requires a 1.8 V ± 5% power supply for V Best practice recommends bypassing the power supply on the PCB with adequate capacitance (>10 μF) and bypassing all power pins with adequate capacitance (0.1 μF) as close to the part as possible ...
Page 13
... See the AN-586 Application Note at information on LVDS. CMOS CLOCK DISTRIBUTION The output drivers of the ADCLK846 can also be configured as CMOS drivers. When selected as a CMOS driver, each output becomes a pair of CMOS outputs. These outputs are 1.8 V CMOS compatible. ...
Page 14
... ADCLK846 www.DataSheet4U.com Termination at the far end of the PCB trace is a second option. The CMOS outputs of the ADCLK846 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in Figure 27. Match the far-end termination network to the PCB trace impedance and provide the desired switching point ...
Page 15
... LFCSP_VQ Evaluation Board Rev Page 0.60 MAX PIN 1 INDICATOR 2.45 EXPOSED 2.30 SQ PAD (BO TT OMVIEW) 2. 0.23 MIN 2.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-24-2 CP-24-2 ADCLK846 ...
Page 16
... ADCLK846 www.DataSheet4U.com NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07226-0-6/09(A) Rev Page ...