MT58L64V36F Micron Semiconductor, MT58L64V36F Datasheet

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MT58L64V36F

Manufacturer Part Number
MT58L64V36F
Description
(MT58LxxxLxxF) 2Mb SRAM
Manufacturer
Micron Semiconductor
Datasheet
NOT RECOMENDED FOR NEW DESIGNS
2Mb SYNCBURST
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (V
• Separate +3.3V or +2.5V isolated output buffer
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL
• Three chip enables for simple depth expansion and
• Clock-controlled and registered addresses, data
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down
• 100-pin TQFP package
• Low capacitive bus loading
• x18, x32, and x36 versions available
OPTIONS
• Timing (Access/Cycle/MHz)
• Configurations
• Packages
• Operating Temperature Range
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_C.p65 – Rev. C, Pub. 11/02
supply (V
WRITE
address pipelining
I/Os and control signals
6.8ns/8.0ns/125 MHz
7.5ns/8.8ns/113 MHz
8.5ns/10ns/100 MHz
10ns/15ns/66 MHz
3.3V I/O
2.5V I/O
100-pin TQFP
Commercial (0°C to +70°C)
128K x 18
128K x 18
64K x 32
64K x 36
64K x 32
64K x 36
DD
Q)
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
MT58L64L36FT-8.5
Part Number Example:
MT58L128V18F
MT58L128L18F
MT58L64V32F
MT58L64V36F
MT58L64L32F
MT58L64L36F
MARKING
None
-6.8
-7.5
-8.5
-10
T
DD
)
FLOW-THROUGH SYNCBURST SRAM
1
MT58L128L18F, MT58L64L32F,
MT58L64L36F; MT58L128V18F,
MT58L64V32F, MT58L64V36F
3.3V V
GENERAL DESCRIPTION
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
18, 64K x 32, or 64K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock
input (CLK). The synchronous inputs include all ad-
dresses, all data inputs, active LOW chip enable (CE#),
two additional chip enables for easy depth expansion
(CE2, CE2#), burst control inputs (ADSC#, ADSP#,
ADV#), byte write enables (BWx#) and global write
(GW#).
(OE#), snooze enable (ZZ) and clock (CLK). There is also
a burst mode pin (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can
be from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
status processor (ADSP#) or address status controller
(ADSC#) input pins. Subsequent burst addresses can be
internally generated as controlled by the burst advance
pin (ADV#).
*JEDEC-standard MS-026 BHA (LQFP).
The Micron
Micron’s 2Mb SyncBurst SRAMs integrate a 128K x
Asynchronous inputs include the output enable
Burst operation can be initiated with either address
2Mb: 128K x 18, 64K x 32/36
DD
, 3.3V or 2.5V I/O, Flow-Through
®
100-Pin TQFP*
SyncBurst
SRAM family employs
©2002, Micron Technology, Inc.

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MT58L64V36F Summary of contents

Page 1

... Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM ™ MT58L128L18F, MT58L64L32F, MT58L64L36F; MT58L128V18F, MT58L64V32F, MT58L64V36F 3. 3.3V or 2.5V I/O, Flow-Through *JEDEC-standard MS-026 BHA (LQFP). GENERAL DESCRIPTION ...

Page 2

NOT RECOMENDED FOR NEW DESIGNS 17 ADDRESS SA0, SA1, SA REGISTER MODE ADV# CLK ADSC# ADSP# BYTE “b” WRITE REGISTER BWb# BYTE “a” WRITE REGISTER BWa# BWE# GW# ENABLE CE# REGISTER CE2 CE2# OE# 16 SA0, SA1, SA MODE ADV# ...

Page 3

NOT RECOMENDED FOR NEW DESIGNS GENERAL DESCRIPTION (continued) Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, ...

Page 4

NOT RECOMENDED FOR NEW DESIGNS ADV# 83 ADSP# 84 ADSC# 85 OE# 86 BWE# 87 GW# 88 CLK CE2# 92 BWa# 93 BWb CE2 ...

Page 5

NOT RECOMENDED FOR NEW DESIGNS TQFP PIN DESCRIPTIONS x18 x32/x36 SYMBOL 32-35, 44-49, 32-35, 44-49, 80-82, 99, 81, 82, 99, 100 100 93 93 BWa BWb# – 95 BWc# – 96 BWd ...

Page 6

NOT RECOMENDED FOR NEW DESIGNS TQFP PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 85 85 ADSC MODE 64 64 (a) 58, 59, (a) 52, 53, 62, 63, 68, 69, 56-59, 62, 63 72 12, (b) ...

Page 7

NOT RECOMENDED FOR NEW DESIGNS INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 ...

Page 8

NOT RECOMENDED FOR NEW DESIGNS TRUTH TABLE OPERATION ADDRESS CE# CE2# CE2 ZZ Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE ...

Page 9

NOT RECOMENDED FOR NEW DESIGNS ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply DD Relative to V .................................... -0.5V to +4.6V SS Voltage Supply DD Relative to V .................................... -0.5V to +4. ............................................... -0. ...

Page 10

NOT RECOMENDED FOR NEW DESIGNS I OPERATING CONDITIONS AND MAXIMUM LIMITS DD (Note: 1) (0°C ≤ T ≤ +70° DESCRIPTION Device selected; All inputs ≤ V Power Supply Cycle time ≥ Current: Operating V = MAX; Outputs ...

Page 11

NOT RECOMENDED FOR NEW DESIGNS TQFP CAPACITANCE DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance Test conditions follow standard test methods (Junction to Ambient) Thermal Resistance (Junction to Top of Case) ...

Page 12

NOT RECOMENDED FOR NEW DESIGNS ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) (0°C ≤ T ≤ +70° +3.3V +0.3V/-0.165V DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times ...

Page 13

NOT RECOMENDED FOR NEW DESIGNS 3.3V I/O AC TEST CONDITIONS Input pulse levels ................. V .................... V Input rise and fall times ..................................... 1ns Input timing reference levels ..................... V Output reference levels ............................ V Output load ............................. See Figures ...

Page 14

NOT RECOMENDED FOR NEW DESIGNS SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced The duration of SNOOZE MODE dictated by the length ...

Page 15

NOT RECOMENDED FOR NEW DESIGNS t KC CLK ADSS t ADSH ADSP# ADSC ADDRESS BWE#, GW#, BWa#-BWd# t CES t CEH CE# (NOTE 2) ADV# OE# ...

Page 16

NOT RECOMENDED FOR NEW DESIGNS t KC CLK ADSS t ADSH ADSP# t ADSS t ADSH ADSC ADDRESS BYTE WRITE signals are ignored when ADSP# is LOW. BWE#, BWa#-BWd# GW# ...

Page 17

NOT RECOMENDED FOR NEW DESIGNS t KC CLK ADSS t ADSH ADSP# ADSC ADDRESS BWE#, BWa#-BWd# t CES t CEH (NOTE 4) CE# (NOTE 2) ADV# OE# D High-Z ...

Page 18

NOT RECOMENDED FOR NEW DESIGNS +0.10 22.10 -0.20 20.10 ±0.10 0.65 TYP +0.06 0.32 -0.10 PIN #1 ID NOTE: 1. All dimensions in millimeters MAX or typical here noted. 2. Package width and length do not include mold protrusion; allowable ...

Page 19

NOT RECOMENDED FOR NEW DESIGNS REVISION HISTORY Added “NOT RECOMENDED FOR NEW DESIGNS,” REV. C, Pub. 11/02, FINAL ........................ November/21/02 Removed 165-pin FBGA package, Rev. 6/01 .................................................................................................. June/7/01 Removed FBGA Part Marking Guide, REV 8/00, FINAL ........................................................................ August/22/00 Changed FBGA ...

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