MT58L64V36F Micron Semiconductor, MT58L64V36F Datasheet - Page 5

• Manufacturer Part Number: MT58L64V36F
• Description: (MT58LxxxLxxF) 2Mb SRAM
• Manufacturer: Micron Semiconductor

NOT RECOMENDED FOR NEW DESIGNS
TQFP PIN DESCRIPTIONS
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_C.p65 – Rev. C, Pub. 11/02
32-35, 44-49, 32-35, 44-49,
80-82, 99,
x18
100
37
36
93
94
87
88
89
98
92
97
86
83
84
–
–
81, 82, 99,
x32/x36
100
37
36
93
94
95
96
87
88
89
98
92
97
86
83
84
SYMBOL
ADSP#
BWa#
BWb#
BWd#
BWE#
ADV#
BWc#
GW#
CE2#
OE#
SA0
SA1
CLK
CE#
CE2
SA
TYPE
Input Synchronous Address Inputs: These inputs are registered and must
Input Synchronous Byte Write Enables: These active LOW inputs allow
Input Byte Write Enable: This active LOW input permits BYTE WRITE
Input Global Write: This active LOW input allows a full 18-, 32-, or 36-bit
Input Clock: This signal registers the address, data, chip enable, byte
Input Synchronous Chip Enable: This active LOW input is used to enable
Input Synchronous Chip Enable: This active HIGH input is used to enable
Input Output Enable: This active LOW, asynchronous input enables the
Input Synchronous Chip Enable: This active LOW input is used to enable
Input Synchronous Address Advance: This active LOW input is used to
Input Synchronous Address Status Processor: This active LOW input
(continued on next page)
meet the setup and hold times around the rising edge of CLK.
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
operations and must meet the setup and hold times around the
rising edge of CLK.
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
write enables and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock’s rising edge.
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
the device and is sampled only when a new external address is
loaded.
the device and is sampled only when a new external address is
loaded.
data I/O output drivers.
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on this pin effectively causes
wait states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
FLOW-THROUGH SYNCBURST SRAM
5
2Mb: 128K x 18, 64K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2002, Micron Technology, Inc.