MT58L256V36F Micron Semiconductor, MT58L256V36F Datasheet

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MT58L256V36F

Manufacturer Part Number
MT58L256V36F
Description
(MT58Lxxxx) 8Mb SYNCBURST SRAM
Manufacturer
Micron Semiconductor
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT58L256V36FF-8.5
Manufacturer:
MICRON/美光
Quantity:
20 000
8Mb SYNCBURST
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (V
• Separate +3.3V or +2.5V isolated output buffer
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL WRITE
• Three chip enables for simple depth expansion and
• Clock-controlled and registered addresses, data I/Os
• Internally self-timed WRITE cycle
• Burst control (interleaved or linear burst)
• Automatic power-down for portable applications
• 100-pin TQFP package
• 165-pin FBGA
• Low capacitive bus loading
• x18, x32, and x36 versions available
OPTIONS
• Timing (Access/Cycle/MHz)
• Configurations
• Packages
• Operating Temperature Range
8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM
MT58L512L18F_C.p65 – Rev. 2/02
supply (V
address pipelining
and control signals
7.5ns/8.8ns/113 MHz
8.5ns/10ns/100 MHz
10ns/15ns/66 MHz
3.3V I/O
512K x 18
256K x 32
256K x 36
2.5V I/O
512K x 18
256K x 32
256K x 36
100-pin TQFP (2-chip enable)
100-pin TQFP (3-chip enable)
165-pin, 13mm x 15mm FBGA
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
DD
Q)
MT58L256V36FT-10
Part Number Example:
MT58L512L18F
MT58L256L32F
MT58L256L36F
MT58L512V18F
MT58L256V32F
MT58L256V36F
MARKING
None
-7.5
-8.5
-10
IT
DD
T
S
F*
)
FLOW-THROUGH SYNCBURST SRAM
1
MT58L512L18F, MT58L256L32F,
MT58L256L36F; MT58L512V18F,
MT58L256V32F, MT58L256V36F
3.3V V
* A Part Marking Guide for the FBGA devices can be found on Micron’s
** Industrial temperature range offered in specific speed grades and
GENERAL DESCRIPTION
speed, low-power CMOS designs that are fabricated us-
ing an advanced CMOS process.
256K x 32, or 256K x 36 SRAM core with advanced syn-
chronous peripheral circuitry and a 2-bit burst counter.
All synchronous inputs pass through registers controlled
by a positive-edge-triggered single-clock input (CLK).
The synchronous inputs include all addresses, all data
inputs, active LOW chip enable (CE#), two additional
chip enables for easy depth expansion (CE2#, CE2), burst
control inputs (ADSC#, ADSP#, ADV#), byte write
Web
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
configurations. Contact factory for more information.
The Micron
Micron’s 8Mb SyncBurst SRAMs integrate a 512K x 18,
site—http://www.micron.com/support/index.html.
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
, 3.3V or 2.5V I/O, Flow-Through
®
SyncBurst
100-Pin TQFP
165-Pin FBGA
SRAM family employs high-
1
©2002, Micron Technology, Inc.

Related parts for MT58L256V36F

MT58L256V36F Summary of contents

Page 1

... Commercial (0°C to +70°C) Industrial (-40°C to +85°C)** Part Number Example: MT58L256V36FT-10 8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM MT58L512L18F_C.p65 – Rev. 2/02 8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM ™ MT58L512L18F, MT58L256L32F, MT58L256L36F; MT58L512V18F, MT58L256V32F, MT58L256V36F 3. MARKING -7.5 -8.5 -10 NOTE: 1. JEDEC-standard MS-026 BHA (LQFP). MT58L512L18F * A Part Marking Guide for the FBGA devices can be found on Micron’ ...

Page 2

ADDRESS SA0, SA1, SAs REGISTER MODE ADV# CLK ADSC# ADSP# BYTE “b” WRITE REGISTER BWb# BYTE “a” WRITE REGISTER BWa# BWE# GW# ENABLE CE# REGISTER CE2 CE2# OE# 18 SA0, SA1, SAs MODE ADV# CLK ADSC# ADSP# BYTE “d” ...

Page 3

GENERAL DESCRIPTION (continued) enables (BWx#) and global write (GW#). Note that CE2# is not available on the T Version. Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) ...

Page 4

TQFP PIN ASSIGNMENT TABLE PIN # x18 x32/x36 PIN # 1 NC NF/DQPc DQc DQc DQc DQc 32 8 ...

Page 5

ADV# 83 ADSP# 84 ADSC# 85 OE# 86 BWE# 87 GW# 88 CLK BWa# 93 BWb CE2 97 CE ...

Page 6

SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK CE2# BWa# BWb CE2 CE ADV# ADSP# ADSC# OE# BWE# GW# CLK CE2# BWa# BWb# BWc# BWd# ...

Page 7

TQFP PIN DESCRIPTIONS x18 x32/x36 SYMBOL 32-35, 44-50, 32-35, 44-50, 80-82, 99, 81, 82, 99, 100 100 92 (T Version Version Version Version BWa BWb# – ...

Page 8

TQFP PIN DESCRIPTIONS (CONTINUED) x18 x32/x36 SYMBOL 84 84 ADSP MODE (a) 58, 59, (a) 52, 53, DQa 62, 63, 68, 69, 56-59, 62, 63 72 12, (b) 68, 69, DQb ...

Page 9

CE# BWb# NC CE2# BWE CE2 NC BWa# CLK GW ...

Page 10

FBGA PIN DESCRIPTIONS x18 x32/x36 SYMBOL 2A, 2B, 3P, 2A, 2B, 3P, 3R, 4P, 4R, 3R, 4P, 4R, 8P, 8R, 9P, 9R, 8P, 8R, 9P, 10A, 10B, 10P, 9R, 10A, 10B, 10R, 11A, 11P, 10P, 10R, ...

Page 11

FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 9A 9A ADV ADSP ADSC MODE (LB0#) (a) 10J, 10K, (a) 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11G 11K, 11L, 11M (b) 1J, ...

Page 12

FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 3C, 3D, 3E, 3C, 3D, 3E, V 3F, 3G, 3J, 3F, 3G, 3J, 3K, 3L, 3M, 3K, 3L, 3M, 3N, 9C, 9D, 3N, 9C, 9D, 9E, 9F, 9G, 9E, 9F, 9G, 9J, 9K, ...

Page 13

INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 PARTIAL TRUTH TABLE FOR ...

Page 14

TRUTH TABLE OPERATION ADDRESS CE# CE2# CE2 Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin ...

Page 15

ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply DD Relative to V ..................................... -0.5V to +4.6V SS Voltage Supply DD Relative to V ..................................... -0.5V to +4. (DQx) .......................................... -0. (inputs) .......................................... ...

Page 16

I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0°C T +70° +3.3V +0.3V/-0.165V DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low ...

Page 17

I OPERATING CONDITIONS AND MAXIMUM LIMITS DD (Note 1) (0°C T +70° +3.3V +0.3V/-0.165V unless otherwise noted DESCRIPTION CONDITIONS Power Supply Device selected; All inputs Current: Operating Cycle time MAX; ...

Page 18

FBGA CAPACITANCE DESCRIPTION Address/Control Input Capacitance Output Capacitance (Q) Clock Capacitance TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance Test conditions follow standard test (Junction to Ambient) methods and procedures for measuring thermal impedance, per EIA/JESD51. Thermal Resistance (Junction to Top of ...

Page 19

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) (0°C T 70° +3.3V +0.3V/-0.165V unless otherwise noted DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid ...

Page 20

I/O AC TEST CONDITIONS Input pulse levels ................. V ................... V Input rise and fall times ..................................... 1ns Input timing reference levels ..................... V Output reference levels ............................ V Output load ............................. See Figures 1 and ...

Page 21

SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced The duration of SNOOZE MODE dictated by the length of time ...

Page 22

KC CLK ADSS t ADSH ADSP# ADSC ADDRESS BWE#, GW#, BWa#-BWd# t CES t CEH CE# (NOTE 2) ADV# OE# t OEQ t KQLZ Q ...

Page 23

KC CLK ADSS t ADSH ADSP# t ADSS ADSC ADDRESS BYTE WRITE signals are ignored when ADSP# is LOW. BWE#, BWa#-BWd# GW# t CES t CEH CE# (NOTE 2) ...

Page 24

KC CLK ADSS t ADSH ADSP# ADSC ADDRESS BWE#, BWa#-BWd# t CES t CEH (NOTE 4) CE# (NOTE 2) ADV# OE# D High-Z Q Q(A1) Q(A2) Back-to-Back READs ...

Page 25

PIN #1 ID 14.00 ±0.10 +0.20 16.00 -0.05 NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst ...

Page 26

BALL A11 165X Ø 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.40 7.50 ±0.05 15.00 ±0.10 7.00 ±0.05 5.00 ±0.05 NOTE: 1. All dimensions in millimeters MAX or typical where noted. ...

Page 27

REVISION HISTORY Removed "Preliminary Package Data" from front page ......................................................................... February 22/02 Removed 119-pin PBGA package and references .................................................................................. February 14/02 Removed note "Not Recommended for New Designs," Rev. 6/01 ................................................................. June 7/01 Added industrial temperature references and notes, Rev. ...

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