MT90812 Mitel Networks Corporation, MT90812 Datasheet
MT90812
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MT90812 Summary of contents
Page 1
... The functional block diagram is shown in Figure 1. An evaluation board, MEB90812, is available complete with software and a user manual, which demonstrates the layout of a typical application board and facilitates the use of the MT90812, and peripheral devices such as Mitel’s DNIC products. MT90812 December 1999 timeslot ...
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... MT90812 STi0 Serial to STi1 Parallel M Converter EST1 U X Conference FSK and Tone Generation D-channel TX/RX Microprocessor CPU Interface C.O. 2B+D 2B+D Trunks 2B+D CODEC MPU Interface - D-channel - Chip control Figure 2 - System Blocks - Typical Configuration 2 Gain Data Output Control Memory Mux Connect Memory Energy Detect Timing & ...
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... PIN MQFP Figure 3 - Pin Connections MT90812 RxCEN 57 TxCEN REOP 56 TEOP 55 VSS1 54 AD7 53 AD6 52 AD5 51 AD4 50 AD3 49 AD2 48 AD1 47 AD0 46 VSS5 45 ...
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... MT90812 Pin Description Pin # Name 64 Pin 68 Pin MQFP PLCC 1 25- Connect. Ground 2-11 27- Address 0 - 9(Input). When non-multiplexed CPU bus is selected, these lines provide the address lines to IDX internal memories DS/RD Data Strobe/Read (Input). For Motorola multiplexed bus operation, this active high DS input works with CS to enable the read and write operations ...
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... Either F8 or FPi are used for frame synchronization depending on the timing mode selected C4i Clock 4.096 MHz (Input). This input is the 4.096 MHz clock input Connect. Ground 50-51 10-11 IC Internal Connect. Open VSSA Analog Ground VDDA +5 Volt Power Supply (Analog). MT90812 Description 5 ...
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... MT90812 devices, 20 three party conferences can be supported, independent of which MT90812 the party originated. For Tone Generation, 6 programmable tones per MT90812 translates to 24 programmable tones in a four MT90812 system, all of which can be routed to any channel in the system. ...
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... Use of Data Memory Reserved for Expansion Bus Streams .................................................................15 6.0 Conferencing ................................................................................................................. 18 6.1 Channel Attenuation...............................................................................................................................20 6.2 Noise Suppression and Channel Inversion ............................................................................................20 6.3 Tone Insertion ........................................................................................................................................20 6.4 Conference Overflow..............................................................................................................................21 6.5 Starting a New Conference ....................................................................................................................21 6.6 Removing a channel from a Conference................................................................................................21 7.0 Gain Control ................................................................................................................... 22 8.0 Delays Through the MT90812 ....................................................................................... 22 8.1 Minimum Delay Mode (CST bit=0) .........................................................................................................22 8.2 Constant Delay Mode (CST bit=1) .........................................................................................................24 8.3 Delays in Conferencing ..........................................................................................................................24 MT90812 vii ...
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... D-Channel Basic Receive Transmit Block................................................................... 30 11.1 Receiver Operation ................................................................................................................................31 11.1.1 Receiver Interrupt Handling............................................................................................................ 32 12.0 Transmitter Operation ................................................................................................... 33 12.1 Transmitter Interrupt Handling................................................................................................................34 13.0 HDLC Resource Allocator Module ............................................................................... 34 13.1 General Description of MT90812 and Shared HDLC Configuration.......................................................35 13.2 Connection to MT8952 HDLC Controller and MT9171/72B DNIC .........................................................35 13.2.1 Connection to MT8952B HDLC Controller ..................................................................................... 35 13.2.2 Connection to MT9171/72B DNIC .................................................................................................. 36 13.2.3 Data Stream Flow........................................................................................................................... 36 13.3 TX Control ..............................................................................................................................................37 13 ...
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... Energy Detect B - High Threshold Register (EDBHT)...........................................................................63 22.17 Supervisory Signal Cadence Register B (SSCB) ..................................................................................63 22.18 Low Tone Coefficient Registers 1-7 (LTC1-7).......................................................................................64 22.19 High Tone Coefficient Registers 1-7 (HTC1-7) ......................................................................................64 22.20 Conference Party Control Register (CPC1-15) .....................................................................................65 22.21 D-Channel Receive Interrupt Threshold (DRXIT)...................................................................................66 22.21.1 Message Length Interrupt Mode.................................................................................................... 66 22.21.2 FIFO Level Interrupt Mode ............................................................................................................ 66 22.22 D-Channel RX Control (DRXC) ..............................................................................................................67 22.23 D-Channel BR Status (DRXS)................................................................................................................68 MT90812 ix ...
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... MT90812 22.24 D-Channel RX FIFO Output (DRXOUT).................................................................................................68 22.25 D-Channel TX FIFO Input (DTXIN) ........................................................................................................68 22.26 D-Channel TX Control (DTXC)...............................................................................................................69 22.27 HRA CTRL Register 1(HC1) ..................................................................................................................70 22.28 HRA CTRL Register 2 (HC2) .................................................................................................................71 22.29 HRA CTRL Register 3 (HC3) .................................................................................................................72 22.30 HRA Lock Out Register 1 (HLO1) ..........................................................................................................72 22.31 HRA Lock Out Register 2 (HLO2) ..........................................................................................................72 22.32 HRA Status 1 (HS1) ...............................................................................................................................73 22.33 HRA Status 2 (HS2) ...............................................................................................................................74 22.34 HRA Status 3 (HS3) ...............................................................................................................................74 22 ...
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... MT90812 devices. For TDM Link mode, the expansion bus is configured as a TDM serial stream which can run at 2.048, 4.096 or 8.192 Mb/s. In TDM Link mode, the MT90812 can be connected to more peripheral devices or to other digital switches (i.e. MT8980/1/2 or MT8985/6) to support larger matrices of MT90812 devices ...
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... Refer to Section 9.2, “Serial Data Interface Timing”. The MT90812 can support Primary Rate or Basic Rate devices. Using the Basic Rate devices (e.g. MT9171/72 DNIC) in dual port mode the D-Channel should be assigned to STi/o1 streams. D-channel signalling support is provided for any timeslot on the STi/o1 streams for the HDLC Controller mode. The DBRT can access any timeslot and stream. Refer to “ ...
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... Which channels are read are also determined from the EBUS position bits. For example, IDX A will read data during timeslots EA1, EA2,... EA32. Each MT90812 will receive a total of 128 channels from the two streams EST0 and EST1. For IDX A, the 96 channels, B1-B32, C1-C32, D1-D32 will be taken from EST0 and 32 channels EA1-EA32 will be taken from EST1. A description of programming the switch in IDX Link mode is given in “ ...
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... Data Transfer from Local TDM Streams to Data Memory The serial data incoming to the MT90812 is converted into parallel format (8 bits per channel) with the parallel to serial converters for both the Local and Expansion Bus streams. This data is written to consecutive locations in Data Memory. ...
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... Control Register and the use of Connection Memory • Connect Memory Configurations for Expansion Bus Modes Each will be described below. A full description of addressing memory in the MT90812 is given in “Address Memory Map” starting on page 12. Refer to Section 21.0 for a definition of the Connection Memory High and Low bits. ...
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... and handles the microprocessor control signals CS, DTA, R/W and DS. The lower order bits(8) originate from the address lines directly. The address lines A6-A0, on the Control Interface, give access to the MT90812 registers directly zero, or depending on the contents of AMS register, to the High or Low sections of the Connection Memory the Data Memory. ...
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... In addition to holding the incoming data from the TDM streams, Data Memory holds the output of the other MT90812 blocks. This is described below in the following section. Expansion Memory page is used to hold the incoming data for the expansion bus TDM streams. Refer to “Use of Data Memory Reserved for Expansion Bus Streams” ...
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... MT90812 Address Local Data Memory A6-A0 40-59 DTMF Tones(26) 59-5A Tone Ringer or DTMF 5B-5E Tones(4) 5F FSK or DTMF 60-6E CONFout(15) 6F unused 70 DCHout(1) 71-7F unused(14) 5.3 Connection Memory use in Conferencing, Gain Control and specifying Incoming Sources for Energy Detect and DBR Connection Memory is used to specify the source and gain for the 64 outgoing channels of STo0 and STo1 and the 128 outgoing channels of the expansion bus. Message mode, Minimum or Constant Delay and Output Enable are specifi ...
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... EP1 and EP0 bits in Control Register B. For example, a group of four MT90812 devices are labelled and D. The 128 channels on the expansion bus streams are identified as A1, B1, C1, D1, A2, B2, C2, D2,...., A128, B128, C128, D128. The MT90812 with EP1,EP0 set to 0,0 will read and write to EST0 and EST1 as listed in Table 5 ...
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... MT90812 FP Expansion Bus EST0 Data Memory Hex A6-A0 DM EST1 00 EA1 01 EA2 - - 1F EA32 20 EB1 21 EB2 - - 3F EB32 40 EC1 41 EC2 - - 5F EC32 60 ED1 61 ED2 - - 7F ED32 Figure 8 - Data Memory Assignment for Expansion Bus Timeslots for EP1,EP0 = 00 FP EST0 . Expansion Bus Data EST1 Memory Hex A6- EA1 01 EA2 ...
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... Connect Memory allocation for the timeslots on EST0 and EST1. For the IDX A, which has EP0,EP1 = 00, the circled timeslots are read as incoming data to Data Memory. The other timeslots are outgoing MT90812 ...
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... Figure 12 - Data Memory Assignment for Expansion Bus Timeslots for EP1,EP0 = 00 6.0 Conferencing The conference block provides conference call capability in the MT90812 and supports a total of 15 parties, distributed over a maximum of 5 conferences. (i.e. 1x15 parties, 3x5 parties, 5x3 parties etc.). A/m-Law companded data from an incoming channel is converted to linear format, applied incoming gain, processed by a dedicated arithmetic unit, applied outgoing conference gain and stored in Data Memory in linear format ...
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... Noise Suppression Channel Inversion 60- Gain Pad Accumulator 1 Accumulator 5 Add / Subtract slot 10 slot 11 slot 12 slot 13 A+B A+B+C 1 frame (32 timeslots) Figure 14 - Four Party Conference Example MT90812 Connect Memory Low High GCin,Inv,NS Incoming Channel Insertion Tone Gain G H slot 14 slot ...
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... MT90812 Data Memory Incoming Channel Incoming Data 60-6E H* Conference Output Control Registers Conf Party Control 30-3E CID,ST,IT,GCout HEX Figure 15 - Conference Control with Conference Party Control Registers and Connect Memory 6.1 Channel Attenuation Channel Attenuation is provided on incoming and outgoing channels that are in a conference. The gain can range from + steps of 1dB, as well for the incoming PCM data and + steps of 3dB for outgoing PCM data overfl ...
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... CONFO register. The Conference ID in this register will not be updated again until it is reset. The register is reset following a read of the register or resetting the conference block or Mt90812 device. Note 1 - The overflow limit is the same whether Ulaw or Alaw companding is used. Following gain adjustment companding will then implement clipping to the Ulaw and Alaw max values of 8031 and 4032 respectively ...
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... Channel information for a particular timeslot n from the input stream is sent to Data Memory in timeslot n+1. Channel information is queued for an output channel n in timeslot n-1. Thus, information entering the MT90812 from timeslot n, cannot be transmitted in the same timeslot n or timeslot n+1, without a frame delay. Information switched to a timeslot of m=n+2 or later will be switched within the same frame ...
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... Expansion Bus Data Rate 2.048 Mb/s 4.096 Mb/s N/A m>=n+2 m>=2n+3 m>=(n+3)/2 Condition for Output switching channel, within same m, range frame 0-31 m>=n+2 0-31 m>=n+2 0-64 0-127 0-31 m>=n+2 0-64 m>=2n+3 0-127 m>=4n+5 0-31 m>=n+2 0-31 m>=(n+3)/2 0-31 m>=(n+5)/4 . =4Mb/s t.s.=1.95 us. t.s .=8Mb/s t.s.=0.975 us MT90812 8.192 Mb/s N/A m>=n+2 m>=4n+5 m>=(n+5)/4 Throughput Throughput Delay if Delay within condition not same frame met m-n t.s . 32-(n-m) t m-n t.s . 32-(n-m) t m-n t.s . 64-(n-m) t m-n t.s . 128-(n-m) t m-n t ...
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... Timing and Clock Control The MT90812 clock control circuitry selects one of five possible input clock and frame pulse references. The input clock can be either 4.092, 8.192, or 16.384 MHz as described in Section 9.1, “Input Timing Reference”. Fig. 16 shows the Clock Control Functional diagram. The clock control circuitry provides an internal master clock of 8 ...
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... The MT90812 requires at least an 8.192 MHz clock internally. When the C4 input clock is selected the 8.192 MHz clock is derived from the PLL not a valid clock reference when the PLL is disabled. Interrupt Enable Register C8 C8FE *04 H C8F WD Interrupt Status Register ...
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... C8P_C16 can be used directly as a clock input with OSC left unconnected. Refer to Section 9.5, “C8P Pin Timing Source”. When C8P is selected, no frame pulse is used and the MT90812 generates F4o and F8o. F4o and F8o can be disabled by setting F4E and F8E bits low in the Output Clocking Control Register (OCC). ...
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... Advance Information The MT90812 generates C4o, F4o, C8, and F8 signals in either ST-Bus or GCI formats as selected by the FPO bit in the Timing Control Register (TC). This selection is independent of the incoming frame synchronization used. 9.2.5 Selecting Timing from the Input Clock Reference or from the PLL As mention above, the clocks used for the local and expansion bus streams can be derived directly from the input clock reference or from the PLL ...
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... C8 clock an interrupt is generated and the C8F bit in the Interrupt Status Register (INTS) is set. The system can service the interrupt and maintain operation of the MT90812 by switching clock input reference from C8 (CR0-1=01) to C8P (CR0-1=10) and enable the MT90812 to supply C8 output. ...
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... Advance Information 9.5 C8P Pin Timing Source The MT90812 can use either a clock or crystal, connecting to pins C8P_C16i and OSCo reference timing source. 9.5.1 Clock Oscillator Fig. 19 shows a 8.192MHz clock oscillator, with 32 ppm tolerance, directly connected to C8P_C16i pin of the MT90812. The output clock should be connected directly (not AC coupled) to the C8P_C16i pin, and the OSCo output should be left open ...
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... Each of the blocks are described in the following sections. 11.0 D-Channel Basic Receive Transmit Block The MT90812 can support communications over the D-channel with the use of the D-channel Basic Receiver/ Transmitter (DBRT). The D-Channel Basic Receiver and Transmitter are used to transfer data between a channel on a serial stream and the parallel micro-port with the use of two 32 byte FIFOs ...
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... STP STP Figure 21 - DBRT modes MT90812 Parity bit Bit Rate bits/frame bits/frame bits/frame bits/frame bits/frame STP STP ...
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... MT90812 will specify whether the received data will have a parity bit and consequently the receiver will perform a parity check on the received data. In FLI Mode, the start and stop bits and the parity bit can be enabled or disabled with the SE and PE bits in the DRXC Control register, respectively. With the start and stop bits enabled, the start of the message is identifi ...
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... Uport Write DTXIN 44 HEX Figure 23 - Data Flow for D-channel Transmitter for the intended output channel. HEX of the Control Register page is used to program the Transmitter HEX Parallel to Serial DBTX TX Connect Memory TX FIFO 70 HEX MT90812 of the HEX . One HEX Output Stream Channel m 33 ...
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... Transmitter interrupts. 13.0 HDLC Resource Allocator Module The HDLC Resource Allocator (HRA) block in the MT90812 provides an interface to the MT8952 HDLC Protocol Controller. This interface supports the sharing of the HDLC resource across several MT9171/72 DNIC devices for communication over the D-Channel. The MSAN-122 application note describes how voice/data channels and signalling information channels on a digital communications link are supported ...
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... Connection to MT8952 HDLC Controller and MT9171/72B DNIC Fig. 24 shows a typical application of the MT90812 connected to a MT8952 HDLC Protocol Controller and several MT9171/72 DNICs. Placing the MT8952B in the External Timing mode and the DNICs in the dual-port digital-network mode allows for easy interface through the HRA block. ...
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... Connect Memory of the MT90812. The C-channel information from Connect Memory is sent out STo1 of the MT90812 along with the D-Channel information from DPER. Stream 2 connects STo1 from the MT90812 to CDSTi of the DNICs. The merging of the D- and C- channels is described in Section 13.3.4. ...
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... D-Channel data from the HDLC controller into the local TDM stream. These functions will be described in the sections below. 13.3.1 Generation of TxCEN The HDLC transmitter is controlled by the MT90812 generated Transmit Clock Enable signal, TxCEN. The TxCEN output signal enables the HDLC transmitter in the appropriate channel as specified by the system, via Crystal Clock 20 ...
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... MT90812 microport. TxCEN output signal is enabled for one to eight bits per channel per frame, depending upon the selected baud rate. The desired active channel is selected by the system via a write to the MT90812 device’s Next Transmit Channel (NTX) bits defined in HRA CTRL Register 3 (HC3). A write to this register will start TxCEN to be enabled for the channel specifi ...
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... Fig. 24. The C-channel information, which have been written to the MT90812 Connect Memory, are assigned to the first 16 channels of STo1, stream #2. The D-channel from the MT8952B is input to the HRA block of the MT90812 at DPER, stream #5, during the times enabled by TxCEN. The C and D-channels are combined to produce STo1, stream #2, which is then routed to the DNICs ...
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... This signal has the same characteristics as TxCEN. The RxCEN signal enables the HDLC receiver in the appropriate channel as specified by the system, via the MT90812 microport. RxCEN is enabled for one to eight bits per channel per frame, depending upon the selected baud rate, specified in HRA CTRL Register 1(HC1). ...
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... RTS is not detected • the channel is the current active receive channel • the channel is locked out • the channel is the current active transmit channel The first, which was described above, is when a flag has not been detected within 15 valid bit times. MT90812 . 41 ...
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... Hence, the C-channel information may change every frame. 16.0 Tone Generation The MT90812 generates the standard 16 DTMF frequencies within +/- 0.6% of the nominal standard frequencies. Table 13 shows the standard DTMF frequencies, the coefficient used to generate the closest frequency, the actual frequency generated and the percent deviation of the generated tone from the nominal. ...
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... Total signal to distortion ratio over this band is at least 30dB. Coefficient Value 0 1-63 250+(Coef x 3.90625) 64-127 128-255 (Coef x 15.625) - 1000 Table 14 - Programmable Frequencies Available Formula Hz Frequency Range Hz Disabled 253.91-496.09 Coef x 7.8125 500.0 - 992.19 1000.0 - 2984.38 MT90812 dB, is provided for outgoing channels Resolution 3.90625 7.8125 15.625 43 ...
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... MT90812 Addr Frequency(Hz) Application 00 697+1209 DTMF digits 1 01 697+1336 DTMF digit 2 02 697+1477 DTMF digit 3 03 697+1633 DTMF digit A 04 770+1209 DTMF digit 4 05 770+1336 DTMF digit 5 06 770+1477 DTMF digit 6 07 770+1633 DTMF digit B 08 852+1209 DTMF digit 7 09 852+1336 ...
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... The FSK transmit memory is a 20-byte FIFO that is accessed at the address 07 addresses indicated in Table 20 on page 53. The FSK output is memory mapped to address 5F Table 3 on page 14. Fig. 26 illustrates the data flow for the FSK transmitter in the MT90812. freq coef ...
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... MT90812 Data Memory 5F H Control Registers Uport Write 07 FSKM FSK modulator that generates two output frequencies, representing the ‘marks’ and ‘spaces’. Start and Stop bits are added to each byte FSK transmitter outputs PCM coded signal. Data is written to the FSK FIFO. Start and Stop bits are added to each byte. The FSK modulator generates two output frequencies, representing the ‘ ...
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... At point B the low threshold limit is crossed, the SSCR register is updated with the new count, t1, and an interrupt is generated. The position of the signal envelope, now below the low threshold, is indicated with the P bit of SSCR set low and high threshold level is programmed in the Energy Detect Low H MT90812 47 ...
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... Energy Detect A Low and High Threshold EDBLT/EDBHT Energy Detect B Low and High Threshold SSCR1/2 Supervisory Signal Cadence Registers Table 18 - Supervisory Signal Detection Registers Refer to MSAN-178 note for Implementing an Algorithm for Interpreting The Measured Cadence of a Call Progress Signal by the MT90812. 48 Delayed interrupt Interrupt D, P= ...
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... CPU Bus connected to the MT90812. This circuit uses the level of the DS/ RD input pin at the rising edge of the AS/ALE to identify the appropriate bus timing connected to the MT90812. If DS/RD is low at the rising edge of AS/ALE then Motorola bus timing is selected. If DS/RD is high at the rising edge of AS/ALE, then Intel bus timing is selected ...
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... MT90812 21.0 Connection Memory Bits Locations in the Connection Memory are associated with the local TDM output streams and the Expansion Bus streams. It also determines whether individual output channels are in Message Mode, allows individual output channel to go into a high-impedance state and specifies the gain control for the outgoing channels. Refer to Section 5.2, “ ...
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... Output from the D-channel TX FIFO buffer. Allows D-channel TX buffer to be directed to any outgoing channel. unused(14) unused(14) Ei1 32 Channels Expansion Bus Block 1 Ei2 32 Channels Expansion Bus Block 2 Ei3 32 Channels Expansion Bus Block 3 Ei4 32 Channels Expansion Bus Block 4 Table 19 - Data Memory Addressing MT90812 Description 51 ...
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... MT90812 22.0 Detailed Register Descriptions The first page of 128 locations of memory contains the control registers. The control registers are accessed independent of the setting of the memory select bits when in multiplexed mode by setting external address bit non-multiplexed mode the control registers are accessed with A7,A8 and A9 set to 1 (as described in Section 5 ...
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... HRA Status 2 HRA Status 3 HRA Status 4 unused(7) reserved must be iniitialized unused(30) Table 20 - Control Registers and 61 respectively. Location MS1 MS2 Description MT90812 Page page 70 page 71 page 72 page 72 page 73 page 73 page 74 page 74 page 75 must be initialized MS0 53 ...
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... MT90812 22.2 Control Register (CTL) The Control register (CTL) selects Data/Connection Memory and defines Expansion bus position. Read/Write Address is: 001 H Reset Value is Bit Name 7 - Unused. 6 Serial Output enable for the serial outputs. If this input is low, STo0, STo1, EST0, EST1 are Stream high impedance ...
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... C16 Selects one of four possible clock references, C4, C8, C8P, or C16 not valid when the PLL is not enabled. The MT90812 requires at least an 8M clock internally. When the C4 input clock is selected the 8.192 Mhz clock is derived from the PLL. When C8P is selected as the input clock reference no frame pulse is used and the MT90812 generates F4o and F8o when they are enabled. Refer to Table 9, “ ...
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... MT90812 22.4 Output Clocking Control Register (OCC) The register is configured as follows: Read/Write Address is: 003 H Reset Value is PCOS Bit Name 7 PCOS PLL Clock Output Select. With PE=1, when PCS = 1 selects clocks generated from the PLL for use in outgoing EST1/0 TDM streams, F8o and C8o. Otherwise the clocks are derived directly from the Input Clock Reference ...
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... Interrupt Status Register (INTS) are still valid but they do not cause the IRQ output to go LOW DTX FTS EDBS EDAS CFS Description DRXE FTE EDBE EDAE CFE DTXE Description MT90812 0 C8F 0 C8FE 57 ...
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... MT90812 22.7 Ringer and FSK Control Register (RFC) The Ringer and FSK Control register (RFC) controls the Ringing Source and FSK Transmitter. The Ringer and FSK control register is configured as follows: Read/Write Address is: 006 H Reset Value is Bit Name 7 RE Ringer Enable bit. ...
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... Conference Party Control registers. Refer to Section 22.20. The Conference ID in this register will not be updated again until it is reset. The register is reset following a read of the register or resetting the conference block or MT90812 device. Following an IRQ being asserted by the conference circuit, the INT would generally be read by the external uP. ...
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... MT90812 22.10 Conference Control Register (CC) The Conference Control register is used in conjunction with the Conference Party Control registers for setting up conferences. The CC register is configured as follows: Read/Write Address is: 009 H Reset Value is Bit Name 7-4 unused 3-1 TD2-0 Tone Duration. Specifies a tone duration from 0.125 seconds to 1.0 seconds in steps of 0 ...
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... The Tone Generation circuit can be enabled with TGE bit set to 1. With the circuit reset there is no output generated for all the 32 tones including the Tone Ringers and FSK transmitter output TGE TRE2 WR2 TRE1 WR1 ERB Description MT90812 0 ERA and ...
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... MT90812 22.12 Energy Detect A - Low Threshold (EDALT) The EDALT register is configured as follows: Read/Write Address is: 011 H Reset Value is Bit Name 7 Unused 6-0 Low Threshold Energy Detect Low Threshold. PCM sign-magnitude format with no sign bit. Bit 6 = MSB. ET0-ET3 encode the PCM step number while ET4-ET6 encode the PCM chord number. ...
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... ET0-ET3 encode the PCM step number while ET4-ET6 encode the PCM chord number. . The continuous signal is indicated by the P bit ET5 ET3 ET6 ET4 ET2 ET1 Description ET5 ET3 ET6 ET4 ET2 Description MT90812 0 ET0 1 0 ET1 ET0 63 ...
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... MT90812 22.17 Supervisory Signal Cadence Register B (SSCB) Read Address is: 016 H Reset Value is Bit Name 7 p Position with respect to high and low thresholds above high threshold below low threshold. 0-6 t6-t0 Cadence of the supervisory signal ranging from 0 to 508 msec in units of 4 msec. ...
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... The conference block provides conference call capability in the MT90812 and supports a total of 15 parties maximum, distributed over conferences, i.e. 1x15 parties, 3x5 parties, 5x3 parties etc. Each of the 15 parties are associated to a conference by programming the corresponding Conference ID number. ...
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... MT90812 The IT bit will be set for the duration of the tone added to the conference. Reading any of the CPC registers in a particular conference, will show the IT bit set for that time. Channel Attenuation is provided on incoming and outgoing channels in a conference. The incoming channel attenuation is set in CMH for the specifi ...
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... In FLI Mode when the ER bit is set the receiver transfers either 1 bits to the RX from Data Memory. If S=1 then the Start and Stop bits are expected on a per byte basis. If S=0 reception starts immediately after ER is set Description MT90812 ...
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... MT90812 22.23 D-Channel BR Status (DRXS) The register is configured as follows: Read Address is Reset Value is Bit Name 7-3 - Unused Overrun Error. Gets set when writing to a full FIFO Parity Error Stop bit Error. 22.24 D-Channel RX FIFO Output (DRXOUT) The register is configured as follows: ...
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... Start Transmitter. ST=1 starts transmission of the message following a write to the TX FIFO. ST=0 clears the FIFO and resets its pointers. The Transmitter Bit Order (TXBO) bit resides in the DRXC register described in Section 22.21 Description MT90812 of the Control Register page. HEX ...
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... MT90812 22.27 HRA CTRL Register 1(HC1) The register is configured as follows: Read/Write Address is Reset Value is SFLAG PRXSEL Bit Name 7 SFLAG Software Controlled Flag Detect (SFLAG). SFLAG is used to allow the system to inject a flag (indicating that a peripheral request-to-send has been detected). This bit can be written asynchronously, has exactly the same effect as the normal fl ...
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... The RX Channel Number selects one of the first 16 timeslots of STi1, with HC1 register bit CD=0, or the last 16 timeslots with bit CD=1. DRX4 is the MSB and DRX1 is the LSB. On reset, these bits are cleared DRX4 DRX3 STEOP DDRX Description MT90812 1 0 DRX2 DRX1 71 ...
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... MT90812 22.29 HRA CTRL Register 3 (HC3) The register is configured as follows: Read/Write Address is Reset Value is Bit Name 7-4 unused Unused. 3-0 NTX4-1 Next TX Channel Number. These bits represent the channel number for the next packet to be transmitted and selects one of the first 16 timeslots of STo1, with HC1 register bit CD=0, or the last 16 timeslots with bit CD=1 ...
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... Reading the channel number via HRA Status register 3 clears the status bit RXCHNL. PRX4-1 represent channels 0-15 on STi1 stream, with HC1 register bit CD=0, or channels with bit CD=1. On reset, channel 0 will be selected, but will be inactive PRX3 CTSACT FLAG PRX4 Description MT90812 PRX2 PRX1 73 ...
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... MT90812 22.33 HRA Status 2 (HS2) The register is configured as follows: Read Address is Reset Value is TXCHNL TXACT Bit Name 7 TXCHNL TX Channel Number Latched (TXCHNL). The next TX channel number in write register 3 has been latched by the TX control circuitry and may be rewritten when this bit is high ...
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... Reading the channel number via this register does not clear the status bit TXCHNL.PTX4-1 represent channels 0-15 on STo1 stream, with HC1 register bit CD=0, or channels with bit CD=1. On reset, channel 0 will be selected, but will be inactive PTX4 PTX3 - - Description MT90812 1 0 PTX2 PTX1 75 ...
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... DNIC and for the DNIC to pass status information back to the system microprocessor. The D-Channel can be transmitted and received on the line with either 8, 16 kbit/s bandwidth. To support this, the MT90812 provides buffering bits per frame to support D-Channel end to end signalling or low speed data transfer. ...
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... Figure 29 - DNIC Time Slot Assignment for STi/o0 and STi/o1 TDM Streams In Figure 28, on page 70, timeslots 4-11 and 20-27 are allocated for the 8 DNICs. Timeslots 4-11 contain the B1 channels on STi/o0 and D-channels on STi/o1. Timeslots 20-27 contain the B2 channels on STi/o0 and C- channels on STi/o1. frame n+1 i+16 i+ i+32 i+ MT90812 77 ...
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... MT90812 24.0 AC/DC Electrical Characteristics Absolute Maximum Ratings* Parameter Voltage on any pin I/O (other than supply pins) 3 Current at any pin other than supply pins 4 Package power dissipation 5 Storage temperature * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ...
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... Sym Min Typ Max t 10 150 F4iS t 20 150 F4iH t 195 244 295 F4iW t 10 F8S t 10 F8H t 50 122 145 F8W MT90812 CMOS Pin Units - V 0.5 0.9 0.1 0.7 0.3 Units Test Conditions ...
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... MT90812 AC Electrical Characteristics - 8.192 MHZ Master Clock Input Characteristics Tolerance Duty cycle † See "Notes" following AC Electrical Characteristics tables. 2.0V C4o 0.8V 3.0V C10o 2.0V * The relative phase between these two clocks is not critical and may vary from 0 to tc4op for MT9171/72/73 DNIC devices. Figure 30 - Frequency Locking for the C4o and C10o Clock ...
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... Figure 32 - C4/F4 Input Clock Reference - GCI Notes: 1. CMOS output 2. TTL input t F4iW t t F4iS F4iH t t f8ol f8oh t t f4ol f4oh t F4iW t t F4iS F4iH t t f8ol f8oh t t f4ol f4oh MT90812 ...
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... MT90812 F8i F4o 1 C4o 1 C2o Figure 33 - C8/F8 Input Clock Reference - ST-Bus Notes: 1. CMOS output 2. TTL input F4o 1 C4o 1 C2o Figure 34 - C8/F8 Input Clock Reference - GCI Notes: 1. CMOS output 2. TTL input 82 t F8W ...
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... C2o Figure 36 - C8P Input Clock Reference - GCI (Timing Control, FPO bit =1) Notes: 1. CMOS output 2. TTL input t t f8ol f8oh t t f4ol f4oh t t f8ol f8oh f4o f4oh MT90812 ...
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... MT90812 C16 c8od F4o t c4od 1 C4o t c2od 1 C2o Figure 37 - C16/F8 Input Clock Reference - ST-Bus Notes: 1. CMOS output 2. TTL input C16 c8od F4o t c4od 1 C4o t c2od 1 C2o Figure 38 - C16/F8 Input Clock Reference - GCI Notes: 1 ...
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... PCS PC0S CLK C4i F4i 1 1 C4o F4o 0 0 C4i F4i 1 1 C4o F4o (Output) (Output) MT90812 diff CLK Rate/ Timing Diagram Data Rate 2 Fig. 40 (ST-Bus) & Fig. 41 (GCI) 2 Fig. 40 (ST-Bus) & Fig. 41 ...
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... MT90812 TDM and Clock Data Rate Control Mode C8/F8, C8P C16 C8/F8, C8P, C16 EBUS 8Mb/s C4/F4 C8/F8, C8P C16/F8 C16/HMVIP C8/F8, C8P, C16 Table 22 - Timing References for TDM Streams * Clock Rate/Data Rate=1, however the incoming data is clocked with the PLL generated clock at 3 quarters into the bit cell. ...
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... ClkP t t stis stih FPW FPH ClkL ClkH t ClkP t stih MT90812 * FP = F4o for Local or EBUS TDM at 2Mb for EBUS at 4 and 8 Mb/s **Clk = C4o, Local or EBUS V TT TDM at 2Mb/s = C8/16 for EBUS at 4 and 8 Mb/s Refer to Timing References for TDM Streams and ...
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... MT90812 t FPW FPS FPH C4i C16 stod 1 EST0 EST1 V L Figure HMVIP Bus Timing for Serial Interface (8.192Mb/s) Notes: 1. CMOS output 2. TTL input AC Electrical Characteristics - HMVIP Bus Timing Characteristics F4i Setup Time ...
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... C8 F8 (Input) (Input C16 F8 (Input) (Input C16 F4 (Input) (Input) MT90812 CLK Rate / Timing Diagram Data Rate 2 Fig. 40 (ST-Bus) & Fig. 41 (GCI Fig. 40 (ST-Bus) & Fig. 41 (GCI) 4 Fig. 40 (ST-Bus) & Fig. 41 (GCI) CLK shown Fig. 42 (ST-Bus) & ...
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... MT90812 AC Electrical Characteristics - Output Delay Parameters Referenced to Input Clock Signals Characteristics Output Driver Enable Delay (2.048, 4.096, 8.192 Mb/s) STo delay, active to active, High active, active to High-Z 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s Sto delay, active to active, High-Z to active, active to High-Z 2.048 Mb/s - Sto0,Sto1 2.048 Mb/s - EST0 4 ...
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... SToD Sym Min Max t STiS STiH MT90812 CLK Rate/ Timing Diagram Data Rate 2 2 Fig. 40 (ST-Bus) & Fig. 41 (GCI Fig. 42 (ST-Bus) & Fig. 43 (GCI) 1* Fig. 40 (ST-Bus) & Fig. 41 (GCI) Units Test Conditions† ...
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... MT90812 24.4 HRA Timing V H F82 FPis FPih V H C82 V L F4o1 t C4od C4o1 t C2od C2o1 V H TEOP2 V L TxCEN1 V H REOP2 V L RxCEN1 V H DPER2 STo1P STo11,3 Figure 47 - The HDLC Controller Related Signals Notes: 1. CMOS output 2. TTL input 3. Refer to STo1 output delay parameters. ...
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... Output Input Jitter Jitter UIpp Frequency kHz 0.100 0.187 4 0.187 5 0.191 6 0.194 8 0.200 10 0.207 15 0.228 20 0.247 25 0.261 28 0.257 30 0.241 34 0.224 36 0.210 40 0.180 45 0.165 50 0.150 60 0.130 70 0.119 80 0.109 90 0.105 100 0.101 200 0.088 MT90812 Conditions/Notes† 12,14-16,21,25,27-32 12,14-16,22,25,27-32 12,14-16,23,25,27-32 12,14-16,24,25,27-32 Conditions/Notes† 12,14-16,22,25,27-32,33 93 ...
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... MT90812 AC Electrical Characteristics - PLL Typical Input to Output Jitter Transfer for Slave Mode Characteristics Jitter at output for Input Jitter Frequency at 0.09UIpp ‡ Typical figures are at 25˚C and are for design aid only: not guaranteed and not subject to production testing. † See "Notes" following AC Electrical Characteristics tables. ...
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... Typical figures are at 25˚C and are for design aid only: not guaranteed and not subject to production testing. † See "Notes" following AC Electrical Characteristics tables. Input Jitter UIpp Input Jitter Frequency kHz Master Slave 1 20.0 20.0 3 8.0 5 5.0 10 1.0 20 1.0 40 0.7 60 0.4 80 0.2 100 0.1 120 0.07 140 0.07 160 0.04 180 0.04 MT90812 Conditions/Notes† 5,12,14-16,22,25,27-32,34 8.0 3.0 0.9 0.5 0.4 0.5 0.3 0.2 0.2 0.2 0.2 0.2 95 ...
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... MT90812 AC Electrical Characteristics - Intel/National - HPC Multiplexed Bus Mode Characteristics 1 ALE pulse width 2 Address setup from ALE falling 3 Address hold from ALE falling 4 RD active after ALE falling 5 Data setup from DTA Low on Read 6 CS hold after RD/ setup from RD 8 Data hold after RD ...
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... DHR t 10 DSH t AKD 95 135 200 + 1/2 C8P 2xC8p + 95 1.5xC8p + AKH t RWS t t ASW DSH ADS ADH SWD ADDRESS ADDRESS t CSS t AKD MT90812 Units Test Conditions† 5 2.0V 0.8V t RWH 2 ...
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... MT90812 AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics setup from DS falling 1 2 R/W setup from DS falling 1 3 Address setup from DS falling 1 4 Address hold after DS falling hold after DS rising 1 6 R/W hold after DS rising 7 Data setup from DTA Low on Read 8 Data hold on read ...
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... C4F4 Input clock reference selected. 28: C8P Input clock reference selected. 29: C8F8 Input clock reference selected. 30: C16F8 Input clock reference selected. 31: C16 Input clock reference and HMVIP selected. 32: Jitter on reference input is 0.008 UIpp. 1UI=244ns. 33: PLL is in Master Mode. 34: PLL is in Slave Mode. MT90812 99 ...
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Package Outlines Dim D General- (lead coplanarity) A Notes Not ...
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