MT90820 Mitel Networks Corporation, MT90820 Datasheet
MT90820
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MT90820 Summary of contents
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... AS R/W DTA D15-D8/ A7-A0 ALE RD WR Figure 1 - Functional Block Diagram MT90820 FAMILY Large Digital Switch (LDX) Advance Information ISSUE 1 Ordering Information MT90820AP 84 Pin PLCC MT90820AL 100 Pin QFP -40 to +85°C ODE STo0 STo1 STo2 Parallel STo3 STo4 to STo5 STo6 Serial STo7 STo8 ...
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... MT90820 CMOS STi0 12 STi1 STi2 14 STi3 STi4 16 STi5 STi6 18 STi7 STi8 20 STi9 STi10 22 STi11 STi12 24 STi13 STi14 26 STi15 FRM 28 FE/HCLK VSS 30 CLK VDD STi0 STi1 82 STi2 STi3 84 STi4 86 STi5 STi6 88 STi7 STi8 90 STi9 STi10 92 STi11 STi12 STi13 94 STi14 96 STi15 ...
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... Read/Write \ Write (Input): In case of non-multiplexed and Motorola multiplexed buses, this input is Read/Write. This input controls the direction of the data bus lines (AD0 - AD7, D8-D15) during a microprocessor access Chip Select (Input): Active low input enabling a microprocessor access of the device. MT90820 CMOS Description 2-181 ...
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... MT90820 CMOS Pin Description Pin # Name 84 100 52 25 AS/ALE Address Strobe or Latch Enable: This input is only used if multiplexed bus is selected CPU Interface Mode (input): If High, this input selects the multiplexed microprocessor bus interface. If this input is not connected or grounded, the device resumes non-multiplexed bus interface. ...
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... The connect memory data is received via the microprocessor interface through the data I/O bus. The addressing of the LDX internal registers, data and connect memories is performed through address input pins and the Memory Select bit in the control register. MT90820 CMOS the source addresses serval ...
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... MT90820 CMOS Serial Data Interface The master clock (CLK) can be either at 4.096, 8.192 or 16.384 MHz allowing serial data link operation at 2.048, 4.096 and 8.192 Mb/s respectively. The master clock frequency is always twice the data rate. The input and output streams accept identical data rate ...
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... This is a potentially hazardous condition when multiple LDXs outputs are tied together to form matrices, as these output may conflict each other. The ODE pin should be held low on power up to keep all outputs in the high impedance condition. MT90820 CMOS 2-185 ...
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... MT90820 CMOS ...
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... Min Typ Max 2 0 100 2 0 MT90820 CMOS Min Max Units 150 . ) unless otherwise stated SS Max Units Test Conditions 5. Units Test Conditions mA ...
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... MT90820 CMOS NOTES: 2-188 Advance Information ...