MT9085 Mitel Networks Corporation, MT9085 Datasheet
MT9085
Available stocks
Related parts for MT9085
MT9085 Summary of contents
Page 1
... Parallel/Serial S30 S31 PAC - Parallel Access Circuit Description The MT9085 Parallel Access Circuit (PAC) provides an interface between an 8 bit, parallel time division multiplexed multiplexed bus. data clocked out on the parallel bus of the Mitel MT9080 (SMX) and output it on 32/16 time division multiplexed serial bus streams ...
Page 2
... MT9085 CMOS VSS S8 S9 S10 S11 S12 S13 VDD VSS S14 S15 S16 S17 S18 S19 S20 S21 2-126 Figure 2 - Pin Connections MCB 58 VSS C2o 55 C4o 54 DFPo 53 VDD 52 VSS 51 C16i 50 F0i ...
Page 3
... Connect Memory Frame Pulse (Output). Framing signal with a nominal 8 kHz frequency; goes low 71 (CKD= (CKD=1) C16 clock cycles before the frame boundary established by F0i. The signal is used by the connection memory in a typical switch configuration. See Figure 15 for timing information. CMOS Description for normal device operation. SS MT9085 2-127 ...
Page 4
... MT9085 CMOS Pin Description (continued) Pin # Name 48 DFPo Data Memory Frame Pulse (Output). Framing signal with nominal 4 kHz frequency; changes state 64 (CKD= (CKD=1) C16 clock cycles after the frame boundary established by F0i. This signal is a complement of DFPo. See Figure 15 for timing information. The signal is used by SMXs (MT9080s) making up the Data Memory in a typical switch configuration ...
Page 5
... Frame Boundary Established by F0i Ch. 31 Bit 0 Ch. 0 Bit 7 Ch. 63 Bit 0 Ch. 0 Bit 7 Frame Boundary Established by F0i Ch. 31 Bit 0 Ch. 0 Bit 7 Ch. 63 Bit 0 Ch. 0 Bit 7 MT9085 CMOS Ch. 0 Bit 6 Ch. 0 Bit 6 Ch. 0 Bit 5 Ch. 0 Bit 6 Ch. 0 Bit 6 Ch. 0 Bit 5 ...
Page 6
... MT9085 CMOS Frame Boundary established by F0i C16i CKD=0 Serial Output Ch. 31, Bit 0 S0-S31 AAA AAAA AAAA AAA AAAA AAAA AAA AAAA AAAA AAA AAAA AAAA Parallel AAA AAAA AAAA AAA AAAA AAAA AAA AAAA AAAA AAA AAAA AAAA Input ...
Page 7
... AAAA AAAA AAAA AA AAA AAAA AAA AAAA AAAA AA AAAA AAA AAAA MT9085 CMOS Ch.0 Bit 6 AAA AAAA AAAA A A AAA AAA AAAA AAAA AAA AAAA AAAA AAA AAA AAAA AAAA AAA AAAA AAAA A AAA AAA AAAA ...
Page 8
... Data is clocked in or out with the C16i clock. Parallel To Serial Conversion The MT9085 can be configured to perform parallel to serial conversion by tying the MCA input high. Data on the eight bit parallel bus (P0-P7) is clocked into the device with the C16i clock clocked out on the serial streams at either 2 ...
Page 9
... Serial to Parallel Conversion The MT9085 can be configured to perform serial to parallel conversion by tying the MCA pin low. single PAC will accept 1024 channels on the serial streams and output the data onto the parallel bus as illustrated in Figure 8. The data on the serial input streams can be clocked ...
Page 10
... MT9085 CMOS In the example configuration shown in Figure 9 the OE pin of PAC #2 is connected to D10 on the Connection Memory. Setting bit 10 high in the Connection Memory location corresponding to a serial channel timeslot will result in the output driver for the specific stream being disabled during that serial channel timeslot ...
Page 11
... For more information, see Mitel’s Application Note MSAN-135, “Design of Large Digital Switching Matrices using the SMX/PAC“ (in this data book) and Application Sheet MSAS-62 “16.384 MHz Clock Generation for SMX/PAC“ (available from Mitel). MT9085 CMOS ...
Page 12
... MT9085 CMOS Timing Source M4 C16 F0i C4i C16i PAC#1a S P0-P7 • • C16 • • • • • • S31 DFPo S31 DFPo 2/4S OE CKD MCA MCB F0 C4 C16 F0i C4i C16i PAC#1b S P0-P7 • • • • • • S31 • ...
Page 13
... MT9085 CMOS Min Max Units -0 -0 -0 -40 125 ° unless otherwise stated. SS Units Test Conditions ° Max Units Test Conditions ...
Page 14
... MT9085 CMOS AC Electrical Characteristics Voltages are with respect to Ground (V ) unless otherwise stated. SS Characteristics 1 C16 Clock Period 2 C4 Clock Period 3 C16 Pulse Width Low 4 C16 Pulse Width High 5 C4 Setup Time 6 Frame Pulse Setup Time 7 Frame Pulse Hold Time † Timing is over recommended temperature & power supply voltages. ...
Page 15
... Data Memory and Connect Memory Frame Pulse (See ) unless otherwise stated. SS ‡ Sym Min Typ Max DFPo CFPo 71 C16 Cycles t CFPD t CFPD t CFPo MT9085 CMOS Units Test Conditions ST-BUS Frame Boundary Established by F0i 64 C16 Cycles t DFPo t DFPo 68 C16 Cycles t ...
Page 16
... MT9085 CMOS AC Electrical Characteristics (See Figure 16) - Voltages are with respect to Ground (V Characteristics 1 Serial Input Setup Time 2 Serial Input Hold Time 3 Serial Output Delay Active to Active High Impedance to Active Active to High Impedance † Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ...
Page 17
... Serial Input and Output Timing in 4 MHz Mode (2/4S=1) ) unless otherwise stated. SS ‡ Sym Min Typ Max Serial Bit Cell MT9085 CMOS Units Test Conditions =150pF =150pF =150pF 2-141 ...
Page 18
... MT9085 CMOS AC Electrical Characteristics to Ground (V ) unless otherwise stated. SS Characteristics 1 Parallel Output Delay 2 Parallel Output Delay High Impedance to Active 3 Parallel Output Delay Active to High Impedance † Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ...
Page 19
... PZA † - Output Enable (OE) Timing, in Parallel to Serial Mode ) unless otherwise stated. SS ‡ Sym Min Typ Max t 2 OES t 10 OEH t OES t OEH t OEH MT9085 CMOS Units Test Conditions ns C =85pF =85pF L Units Test Conditions OES t OEH t OES 2-143 ...
Page 20
... MT9085 CMOS NOTES: 2-144 ...