MT90863 Mitel Networks Corporation, MT90863 Datasheet
MT90863
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MT90863 Summary of contents
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... The MT90863 also offers a sub-rate switching configuration which allows 2-bit wide 16kb/s data channels to be switched within the device. The device has features (such as: message mode; ...
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... MT90863 VDD 97 STio0/FEi0 STio1/FEi1 99 STio2/FEi2 STio3/FEi3 101 STio4/FEi4 STio5/FEi5 103 STio6/FEi6 STio7/FEi7 105 VSS VDD 107 STio8/FEi8 STio9/FEi9 109 STio10/FEi10 STio11/FEi11 111 STio12/FEi12 STio13/FEi13 113 STio14/FEi14 STio15/FEi15 115 VSS VDD 117 STio16/FEi16 STio17/FEi17 119 STio18/FEi18 STio19/FEi19 121 STio20/FEi20 STio21/FEi21 123 ...
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... This pin accepts a 16.384 MHz clock. F0i Master Frame Pulse (5V Tolerant Input): In ST-BUS mode, this input accepts a 61ns wide negative frame pulse Bus mode, it accepts a 122ns wide negative frame pulse. In HMVIP mode, it accepts a 244ns wide negative frame pulse. MT90863 ...
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... Connect to V for normal operation. SS Device Reset (5V Tolerant Input): This input (active LOW) puts the MT90863 in its reset state. This clears the device’s internal counters and registers. It also brings microport data bus STio0 - 31 and STo0 - high impedance state. IC2 Internal Connection 2 (3 ...
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... Mb/s with 32 channels per stream respectively. In 8Mb/s mode, these outputs have data rates of 8.192 Mb/s with 128 channels per stream Serial Output Streams (5V Tolerant Three-state Outputs): In 2Mb/s or Sub-rate Switching mode, these outputs have data rates of 2.048Mb/s with 32 channels per stream MT90863 Description 5 ...
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... Functional Description A functional Block Diagram of the MT90863 is shown in Figure 1. One end of the MT90863 is used to interface with backplane applications, such as HMVIP or H.100 environments, while the other end supports the local switching environments. ...
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... Channel Channel Channel Channel Channel Channel Channel MT90863 Channel 127 Channel Channel Channel 127 1 0 Bit 1 Channel 127 ...
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... OFn bit programming. Table 12 and Figure programming. Serial Input Frame Alignment Evaluation The MT90863 provides the frame evaluation inputs, FEi0 to FEi23, to determine different data input delays with respect to the frame pulse F0i. By using the frame evaluation input select bits (FE0 to FE4) of Advance Information ...
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... Not available STo0 - 11 2.048 Mb/s STo12 Sub-rate Switching Output Stream at 2.048Mb/s STo13 - 15 Not available STi0 - 3 8.192 Mb/s STi4 - 15 Not available STo0 - 3 8.192 Mb/s STo4 - 15 Not available MT90863 HMVIP Mode 244ns 4.096MHz Data Rate 2.048 Mb/s 2.048 Mb/s 4.096 Mb/s 4.096 Mb/s 8.192 Mb/s Not available 8.192 Mb/s Not available 2.048 Mb/s 8.192 Mb/s ...
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... Register which are read only. Memory Mapping The address bus on the microprocessor interface selects the internal registers and memories of the MT90863. If the A7 address input is low, then the registers are addressed shown in Table 4. If the A7 is high, the remaining address input lines ...
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... 126 127 Table 4 - Address Memory Map MT90863 Location Note 2) ( Note 3) ...
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... Frame Alignment Timing and Switching Configurations sections. The control register is used to control the switching operations in the MT90863. It selects the internal memory locations that specify the input and output channels selected for switching. Control register data consists of: the memory block programming bit (MBP): the memory select bits (MS0-2) ...
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... ST-BUS Mode 2Mb/s Sub-rate Switching Mode 8Mb/s ST-Bus Mode Backplane Switching Mode 2Mb/s ST-BUS Mode 2Mb/s CT Bus Mode 4Mb/s ST-BUS Mode 4Mb/s CT Bus Mode 8Mb/s ST-BUS Mode 8Mb/s CT Bus Mode HMVIP Mode MT90863 STA4 STA3 STA2 STA1 ...
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... Initialization of the MT90863 During power up, the TRST pin should be pulsed low, or held low continuously, to ensure that the MT90863 is in the normal operation mode resistor can be connected to this pin so that the device will not enter the JTAG test mode during power up ...
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... Table 8 - Internal Mode Selection (IMS) Register Bits 0000 . BBPD BBPD LBPD LBPD BBPD Description STio0 - 31, STo0 - High impedance state 0 1 Enable 1 1 Enable X 0 Per-channel high impedance MT90863 LBPD LBPD BPE OSB SFE ...
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... MT90863 Read/Write Address: Reset Value FE4 FE3 FE2 FE1 FE0 Bit Name 15-11 FE4-0 Frame Evaluation Input Select. The binary value expressed in these bits refers to the frame evaluation inputs, FEi0 to FEi23. 10 CFE Complete Frame Evaluation. When CFE = 1, the frame evaluation is completed and bits FD9 to FD0 bits contains a valid frame alignment offset ...
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... IF221 IF220 DLE22 IF212 IF211 IF210 DOS5 register Description DLEn =0, if clock rising edge is at the 3/4 point of the bit cell. DLEn =1, if clock falling edge is at the 3/4 point of the bit cell. MT90863 IF10 DLE1 IF02 IF01 IF00 ...
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... MT90863 Input Stream Offset No clock period shift (Default) + 0.5 clock period shift +1.0 clock period shift +1.5 clock period shift +2.0 clock period shift +2.5 clock period shift +3.0 clock period shift +3.5 clock period shift +4.0 clock period shift +4.5 clock period shift Table 11 - Offset Bits (IFn2, IFn1, IFn0, DLEn) & Input Offset Bits (FD9, FD2-0) ...
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... OF10 OF09 OF08 OF07 OF06 OF05 FOR0 register OF23 OF22 OF21 FOR1 register Description Bit 7 Bit 7 Bit 7 Bit 7 MT90863 OF04 OF03 OF02 OF01 OF00 OF20 OF19 OF18 OF17 OF16 offset=0 offset=1 ...
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... MT90863 Read/Write Address: 0C Reset value: 0000 CDA RS WS CA6 Bit Name 15 unused Reserved 14 CDA Complete Data Access. This bit is read only. This bit changes from when data transfer is completed between memory and the data read register or data write register. When the bit in this register is changed from this bit is reset to zero ...
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... BCAB BSAB BSAB BSAB BSAB BCAB Description BSAB3 to BSAB0 Bits Used to Determine the Source Stream of the connection STi0 to STi15 STi0 to STi3 STi0 to STi12 MT90863 RD5 RD4 RD3 RD2 RD1 RD0 BCAB BCAB BCAB ...
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... MT90863 Data Rate 2.048 Mb/s 8.192 Mb/s 2.048 Mb/s Sub-rate Switching Table 18 -. BCAB Bits Programming for Different Data Rates LSAB L/B BV/C BMC OE 4 Bit Name 15 L/B Local/Backplane Select When 1, the output channel of STo0-15 comes from STi0-15 (local) When 0, the output channel of STo0-15 comes from: ...
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... Description Bit7-6 will be the output of the subrate switching stream Bit5-4 will be the output of the subrate switching stream Bit3-2 will be the output of the subrate switching stream Bit1-0 will be the output of the subrate switching stream MT90863 LSR1 ...
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... The LSB bit in the device identification register is the first bit clock out. The MT90863 scan register contains 212 bits. Bit 0 in Table 23 Boundary Scan Register is the first bit clocked out. All tri-state enable bits are active high. ...
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... STio18/FE18 71 STio19/FE19 72 STio20/FE20 73 STio21/FE21 74 STio22/FE22 75 STio23/FE23 76 STio24 STio25 STio26 STio27 STio28 STio29 STio30 STio31 RESET Table 23 - Boundary Scan Register Bits MT90863 Boundary Scan Bit 0 to Bit 213 Output Input Scan Cell Scan Cell ...
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... MT90863 Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Input Voltage 3 Output Voltage 4 Package power dissipation 5 Storage temperature * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Characteristics 1 Operating Temperature 2 Positive Supply 3 Input High Voltage ...
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... HFPS t 50 150 HFPH t 244 HCP t 122 HCH t 122 HCL -10 10 DIF t -10 10 DC4O MT90863 Units Notes ns ST-BUS mode ST-BUS, CT Bus or HMVIP mode Bus mode HMVIP mode ...
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... MT90863 AC Electrical Characteristics - Serial Streams for Backplane and Local Interfaces Characteristic 1 STio/STi Set-up Time 2 STio/STi Hold Time 3 STo Delay - Active to Active 4 STo delay - Active to High-Z - High-Z to Active 5 Output Driver Enable (ODE) Delay Note: 1. High Impedance is measured by pulling to the appropriate rail with R ...
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... Bit SIS8 SIH8 Bit 0, Ch 127 Bit Bit SOD4 Bit SIS4 SIH4 Bit Bit SOD2 Bit Bit Bit MT90863 C8H ...
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... MT90863 F0i C4i/C8i 4.096MHz C16i 16.384MHz F0o C4o 4.096MHz STio (8Mb/s) Bit 1, Ch 127 output STio (8Mb/s) Bit 1, Ch 127 input STio (2Mb/s) output STio (2Mb/s) input Figure 13 - HMVIP Bus Timing for Stream rate of 2.048 Mb/s or 8.192 Mb/s CLK t DZ Valid Data STo ...
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... AKD_MEM t AKH , with timing corrected to cancel time taken to discharge CSS t RWS t ADS VALID ADDRESS VALID READ DATA t t DSW SWD VALID WRITE DATA t DDR t AKD MT90863 Test Max Units Conditions =50pF L 16 440 =50pF, ...
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... REF 30 Typ. C Seating Plane Package Outlines 1.00(3X) REF. Ø 23.00 Note: All governing dimensions are in millimetres for design purposes Ball Gate Array 120-BGA 144-BGA MT90823 0.75 0.15 (169X) Ø 1.50 18.00 0.20 160-BGA MT90863 MT90826 ...
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Index Pin 1 44-Pin Dim Min Max A - 0.096 (2.45) A1 0.01 - (0.25) A2 0.077 0.083 (1.95) (2.10) b 0.01 0.018 (0.30) (0.45) D 0.547 BSC (13.90 BSC) D 0.394 BSC 1 ...
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Package Outlines 160-Pin Dim Min 0.125 (3.17) b 0.009 (0.22) D 1.23 BSC (31.2 BSC) D 1.102 BSC 1 (28.00 BSC) E 1.23 BSC (31.2 BSC) E 1.102 BSC 1 (28.00 BSC) e 0.025 BSC (0.65 ...
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North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no liability for errors ...