SST89V58RD Silicon Storage Technology, SST89V58RD Datasheet - Page 29

• Manufacturer Part Number: SST89V58RD
• Description: FlashFlex51 MCU
• Manufacturer: Silicon Storage Technology

www.DataSheet4U.com
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
SPI Control Register (SPCR)
SPI Status Register (SPSR)
©2006 Silicon Storage Technology, Inc.
Location
Location
D5H
AAH
Symbol
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1, SPR0
Symbol
SPIF
WCOL
SPIE
SPIF
7
7
WCOL
SPE
6
Function
If both SPIE and ES are set to one, SPI interrupts are enabled.
SPI enable bit.
0: Disables SPI.
1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1.4, P1.5, P1.6, P1.7.
Data Transmission Order.
0: MSB first in data transmission.
1: LSB first in data transmission.
Master/Slave select.
0: Selects Slave mode.
1: Selects Master mode.
Clock Polarity
0: SCK is low when idle (Active High).
1: SCK is high when idle (Active Low).
Clock Phase control bit. The CPHA bit with the CPOL bit control the clock and data
relationship between master and slave. See Figures 6-5 and 6-6.
0: Shift triggered on the leading edge of the clock.
1: Shift triggered on the trailing edge of the clock.
SPI Clock Rate Select bits. These two bits control the SCK rate of the device
configured as master. SPR1 and SPR0 have no effect on the slave. The relationship
between SCK and the oscillator frequency, f
6
Function
SPI Interrupt Flag.
Upon completion of data transfer, this bit is set to 1.
If SPIE =1 and ES =1, an interrupt is then generated.
This bit is cleared by software.
Write Collision Flag.
Set if the SPI data register is written to during data transfer.
This bit is cleared by software.
SPR1
0
0
1
1
DORD
5
5
-
SPR0
0
1
0
1
MSTR
4
4
-
29
SCK = f
CPOL
3
3
-
OSC
128
16
64
4
divided by
CPHA
OSC
2
2
-
, is as follows:
SPR1
1
1
-
SPR0
0
0
-
S71255-05-000
Reset Value
Reset Value
Data Sheet
00xxxxxxb
00H
5/06