ISL12029 Intersil Corporation, ISL12029 Datasheet - Page 16

• Manufacturer Part Number: ISL12029
• Description: Real Time Clock/Calendar
• Manufacturer: Intersil Corporation

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OPTION 2 - LEGACY POWER CONTROL MODE
(DEFAULT)
The Legacy Mode follows conditions set in X1226 products.
In this mode, switching from VDD to VBAT is simply done by
comparing the voltages and the device operates from
whichever is the higher voltage.
To select the Option 2, BSW bit in the Power Register must
be set to “BSW = 1”
• Normal Mode (V
To transition from the V
conditions must be met:
V
• Battery Backup Mode (V
The device will switch from the V
following condition occurs:
V
The Legacy Mode power control conditions are illustrated in
Figure 15.
DD
DD
V
FIGURE 14. BATTERY SWITCHOVER WHEN V
FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE
BAT
V
V
V
< V
> V
TRIP
BAT
DD
BAT
BAT
+V
- V
V
TRIP
BATHYS
BATHYS
OFF
DD
) to Battery Backup Mode (V
BATTERY BACKUP
DD
V
DD
to V
BAT
MODE
16
) to Normal Mode (V
BAT
BAT
mode, the following
VOLTAGE
to V
DD
V
TRIP
mode when the
BAT
+ V
ON
TRIPHYS
BAT
> V
DD
3.0V
2.2V
)
)
TRIP
IN
ISL12029
Power-on Reset
Application of power to the ISL12029 activates a Power-on
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
- It prevents the system microprocessor from starting to
- It prevents the processor from operating prior to
- It allows time for an FPGA to download its configuration
- It prevents communication to the EEPROM, greatly
When V
typically 250ms the circuit releases RESET, allowing the
system to begin operation. Recommended slew rate is
between 0.2V/ms and 50V/ms.
Watchdog Timer Operation
The watchdog timer timeout period is selectable. By writing a
value to WD1 and WD0, the watchdog timer can be set to 3
different time out periods or off. When the Watchdog timer is
set to off, the watchdog circuit is configured for low power
operation (See Table 7).
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of SDA
when the SCL line is high (START condition). The start
signal restarts the watchdog timer counter, resetting the
period of the counter back to the maximum. If another
START fails to be detected prior to the watchdog timer
expiration, then the RESET pin becomes active for one reset
time out period. In the event that the start signal occurs
during a reset time out period, the start will have no effect.
When using a single START to refresh watchdog timer, a
STOP condition should be followed to reset the device back
to stand-by mode. See Figure 3.
operate with insufficient voltage.
stabilization of the oscillator.
prior to initialization of the circuit.
reducing the likelihood of data corruption on power up.
WD1
1
1
0
0
DD
exceeds the device V
WD0
1
0
1
0
TABLE 7.
RESET
DURATION
threshold value for
disabled
250ms
750ms
1.75s
April 17, 2006
FN6206.4