ISL24006 Intersil Corporation, ISL24006 Datasheet
ISL24006
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ISL24006 Summary of contents
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... TFT-LCD displays. The 14-channel programmable switchable configuration allows switching between two gamma curves. The ISL24006 is divided into two banks of seven generators: one designed to cover the range from V the remaining seven channels covering the range from ...
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... IL F Clock Frequency CLK R S Input Resistance SDIN DIN t Setup Time S t Hold Time H 2 ISL24006 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD or +7V (max) Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C S Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150° 15V 5V 14V, V VDD ...
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... Block Diagram OSC INT/EXT OSCILLATOR MUX SCL MUX INTERFACE SDA STD_REG A0 ANALOG AVDD POWER DIGITAL DVDD POWER REFERENCE BG GENERATOR 3 ISL24006 VREFU_L VREFU_H 0 DELAY 1 S/H S/H S/H S/H S/H B S/H BANKA DAC HI S S/H BANKA DAC LO LO S/H S/H S/H S/H S/H S/H VREFL_H VREFL_L OUT REFU_H MUX OUT1 S/H MUX OUT2 ...
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... VREFL_H 27 VREFL_L OUT REFU_L 32, 33, 34, 35, 36, OUT1 - OUT7 37 ISL24006 PIN TYPE Analog Output Analog output of V REFU_H Analog Power Power supply for analog circuit Logic Input Selects mode, high = standard, low = register 2 Logic Input I C device address input, bit 0; when LO, hex address = 74; when HI, hex ...
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STANDARD MODE (STD/REG=HIGH) WRITE MODE Start Device Address W A Control Byte DATA SDA SDA Out A 1 ...
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... The ISL24006 uses a simple two-wire I program all 14 outputs. The bus line SCLK is the clock signal line and bus SDA is the bi-directional data information signal line. The ISL24006 can support a clock rate up to 400kHz. An external pull up typically 1kΩ resistor is required for each bus line. ...
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... ISL24006. The first 6 bits (A6 to A1, MSBs) of the device address have been factory programmed and are always 111010. Only the least significant bit (LSB allowed to change the logic state ...
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... Clock Oscillator The ISL24006 require an internal clock or external clock to refresh its outputs. The outputs are refreshed at the falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn't be changed at the rising edges of the OSC clock. Otherwise, it will generate a voltage error at the outputs ...
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... Good printed circuit board layout is necessary for optimum performance. A low impedance and clean analog ground plane should be used for the ISL24006. The traces from the two ground pins to the ground plane must be very short. The thermal pad should be connected to the analog ground plane. Lead length should be as short as possible and all power supply pins must be well bypassed. A 0.1µ ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 ISL24006 FN6110.1 September 9, 2005 ...