ISL6140 Intersil Corporation, ISL6140 Datasheet - Page 2

• Manufacturer Part Number: ISL6140
• Description: Negative Voltage Hot Plug Controller
• Manufacturer: Intersil Corporation

Pin Description
PWRGD (ISL6140; L Version) Pin 1 - This digital output is
an open-drain pull-down device. The Power Good
comparator looks at the DRAIN pin voltage compared to the
internal VPG reference (VPG is nominal 1.7V); this
essentially measures the voltage drop across the external
FET and sense resistor. If the voltage drop is small (<1.7V is
normal), the PWRGD pin pulls low (to VEE); this can be
used as an active low enable for an external module. If the
voltage drop is too large (>1.7V indicates some kind of short
or overload condition), the pull-down device shuts off, and
the pin becomes high impedance. Typically, an external pull-
up of some kind is used to pull the pin high (many brick
regulators have a pull-up function built in).
PWRGD (ISL6150; H Version) Pin 1 - This digital output is
a variation of an open-drain pull-down device. The Power
Good comparator is the same as described above, but the
polarity of the output is reversed, as follows:
If the voltage drop across the FET is too large (>1.7V), the
open drain pull-down device will turn on, and sink current to
the DRAIN pin. If the voltage drop is small (<1.7V), a 2nd
pull-down device in series with a 6.2K resistor (nominal)
sinks current to VEE; if the external pull-up current is low
enough (<1mA, for example), the voltage drop across the
resistor will be big enough to look like a logic high signal (in
this example, 1mA * 6.2kΩ = 6.2V). This pin can thus be
used as an active High enable signal for an external module.
Note that for both versions, although this is a digital pin
functionally, the logic high level is determined by the external
pull-up device, and the power supply to which it is
connected; the IC will not clamp it below the VDD voltage.
Therefore, if the external device does not have its own
clamp, or if it would be damaged by a high voltage, then an
external clamp might be necessary.
OV (Over-Voltage) Pin 2 - This analog input compares the
voltage on the pin to an internal voltage reference (nominal
1.223V). When the input goes above the reference (low to
high transition), that signifies an OV (Over-Voltage)
condition, and the GATE pin is immediately pulled low to
shut off the external FET. Since there is 20mV of nominal
hysteresis built in, the GATE will remain off until the OV pin
drops below a 1.203V (nominal) high to low threshold. A
typical application will use an external resistor divider from
VDD to VEE, to set the OV level as desired; a three-resistor
divider can set both OV and UV.
UV (Under-Voltage) Pin 3 - This analog input compares the
voltage on the pin to an internal voltage reference (nominal
1.223V). When the input goes below the reference (high to
low transition), that signifies an UV (Under-Voltage)
condition, and the GATE pin is immediately pulled low to
shut off the external FET. Since there is 20mV of nominal
hysteresis built in, the GATE will remain off until the UV pin
rises above a 1.243V (nominal) low to high threshold. A
2
ISL6140, ISL6150
typical application will use an external resistor divider from
VDD to VEE, to set the UV level as desired; a three-resistor
divider can set both OV and UV.
If there is an Over-Current condition, the GATE pin is latched
off, and the UV pin is then used to reset the Over-Current
latch; the pin must be externally pulled below its trip point,
and brought back up (toggled) in order to turn the GATE
back on (assuming the fault condition has disappeared).
VEE Pin 4 - This is the most Negative Supply Voltage, such
as in a -48V system. Most of the other signals are
referenced relative to this pin, even though it may be far
away from what is considered a GND reference.
SENSE Pin 5 - This analog input measures the voltage drop
across an external sense resistor (between SENSE and
VEE), to determine if the current exceeds an Over-Current
trip point, equal to nominal (50mV / Rsense). Noise spikes of
less than 2µs are filtered out; if longer spikes need to be
filtered, an additional RC time constant can be added to
stretch the time (See Figure 29; note that the FET must be
able to handle the high currents for the additional time). To
disable the Over-Current function, connect the SENSE pin
to VEE.
GATE Pin 6 - This analog output drives the gate of the
external FET used as a pass transistor. The GATE pin is
high (FET is on) when UV pin is high (above its trip point);
the OV pin is low (below its trip point), and there is no Over-
Current condition (VSENSE - VEE <50mV). If any of the 3
conditions are violated, the GATE pin will be pulled low, to
shut off the FET.
The Gate is driven high by a weak (-45µA nominal) pull-up
current source, in order to slowly turn on the FET. It is driven
low by a strong (32mA nominal) pull-down device, in order to
shut off the FET very quickly in the event of an Over-Current
or shorted condition.
DRAIN Pin 7 - This analog input compares the voltage of
the external FET DRAIN to the internal VPG reference
(nominal 1.7V), for the Power Good function.
Note that the Power Good comparator does NOT turn off the
GATE pin. However, whenever the GATE is turned off (by
OV, UV or SENSE), the Power Good Comparator will usually
then switch to the power-NOT-good state, since an off FET
will have the supply voltage across it.
VDD Pin 8 - This is the most positive Power Supply pin. It
can range from +10 to +80V (Relative to VEE). If operation
down near 10V is expected, the user should carefully
choose a FET to match up with the reduced GATE voltage
shown in the spec table.